Processor Power State Controller for Static Leakage Reduction
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Solution Overview
Problem
Existing CPU power management techniques, such as ACPI C1-C5 states, are insufficient in eliminating static power consumption, especially with advanced CPU manufacturing processes, and transitioning to and from low-power states like C6-state is inefficient, leading to increased power consumption and performance limitations.
Innovation Solution
A controller is used to manage the transition of processor cores to specific power states, including zero-volt states, by monitoring system characteristics and facilitating transitions based on performance and power biases, allowing for efficient entry and exit from C6-state to reduce overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If CPU transitions to low-power states (C1-C5), then dynamic power consumption is eliminated and static power is reduced, but transition efficiency is poor and overall power management is limited
Solution Approach 1:
The patent applies preliminary action by predicting future CPU workload and power state requirements before actual transitions occur. The machine learning model analyzes historical performance data and current system state to preemptively determine optimal power state transitions, avoiding reactive transitions that cause performance degradation. This allows the system to prepare for transitions in advance, improving both power efficiency and transition smoothness.
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring CPU performance metrics, power consumption data, and workload characteristics. This feedback is fed into the machine learning model to refine predictions and adjust power state transitions dynamically. The system learns from past transition outcomes and optimizes future decisions, creating a closed-loop control system that balances power savings with performance requirements.
2Productivity
If CPU manufacturing process is advanced with smaller transistor geometry, then processing performance is improved, but static power (leakage) increases significantly
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting CPU operating parameters including voltage, frequency, and power state based on predicted workload requirements. The machine learning model determines optimal voltage-frequency points and power states that maintain processing performance while minimizing static power consumption. This allows the system to exploit advanced manufacturing benefits while compensating for increased leakage through intelligent parameter optimization.
Solution Approach 2:
The patent implements dynamics by making the CPU power management system adaptive and flexible rather than static. The machine learning model continuously adjusts power state transitions, voltage levels, and frequency scaling based on real-time predictions of workload characteristics. This dynamic approach allows the system to respond to changing conditions and optimize the trade-off between performance and power consumption for advanced process technologies.
3Loss of energy
If CPU enters zero-volt state (C6) to eliminate all power consumption, then power savings are maximized, but transition time and system responsiveness decrease
Solution Approach 1:
The patent applies preliminary action by predicting whether a zero-volt state transition will be beneficial before initiating it. The machine learning model analyzes workload patterns, predicted idle duration, and system state to determine if entering C6 state will result in net power savings. By making predictions in advance, the system avoids premature transitions to zero-volt state that would cause unnecessary performance degradation and延长 transition times.
Solution Approach 2:
The patent implements partial action by not always transitioning to the deepest power state (C6) even when power savings are desired. Instead, the machine learning model selects from a range of power states (C1-C6) based on predicted requirements, sometimes choosing intermediate states that provide adequate power savings with faster transition times. This partial approach to power state selection optimizes the trade-off between maximum power savings and transition efficiency.
Data Source
AI summary
A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.