Processor Power State Tying Logic for Platform Energy Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computer platform power management techniques fail to correlate processor power state transitions with other device power state transitions, leading to inefficiencies in overall platform power management.
Innovation Solution
A method that ties processor-specific power state transitions with device-specific power state transitions through a processor governor and system governor, utilizing tying logic to identify and implement platform-wide system power states, optimizing power management across the platform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate power management determinations are used for processor and devices, then device independence and simplicity are maintained, but platform-wide power efficiency is reduced
Solution Approach 1:
The patent merges separate power management determinations for the processor and devices into a unified platform-wide power state transition mechanism. The tying logic correlates processor power state transitions with device power state transitions, combining previously independent power management operations into a coordinated system that evaluates and transitions the entire platform to appropriate power states together, thereby improving overall platform power efficiency.
Solution Approach 2:
The tying logic acts as an intermediary component that receives power state transition requests from the processor power management and coordinates with device power management. This intermediary correlates the transitions, determines appropriate platform-wide power states, and ensures synchronized transitions across all platform components, resolving the contradiction by adding coordination without overwhelming complexity.
2Productivity
If processor power state transitions are made independent of device power state transitions, then transition speed and responsiveness are improved, but overall platform power optimization is lost
Solution Approach 1:
The tying logic performs preliminary correlation of processor and device power state transitions before actual transitions occur. By evaluating and coordinating power state changes in advance, the system can prepare platform-wide power state transitions that maintain speed while ensuring energy efficiency, as the coordination overhead is performed proactively rather than reactively during the transition itself.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states.