Processor Program Counter Increment via Predecode Bits
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Solution Overview
Problem
Existing processor technologies face challenges in efficiently merging sequential execution processes of RISC processors with parallel execution processes of VLIW control units, leading to worsened processing efficiency and compatibility issues with software resources.
Innovation Solution
A processor design that includes an instruction fetch portion, an instruction predecoder, and a program counter management portion to facilitate the simultaneous fetching and predecoding of instructions, allowing for flexible increment values of the program counter based on predecoded fields, enabling efficient merging of RISC and VLIW processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If subroutine instruction codes are used to designate program numbers for VLIW control unit execution, then parallel execution can be achieved, but all subroutine programs must be prepared in advance and RISC processor processes and VLIW control unit processes are performed in a mutually exclusive manner
Solution Approach 1:
The patent pre-decodes specific fields in instructions during the instruction fetch stage, before full decoding occurs. This preliminary action enables the program counter management portion to determine the appropriate increment value in advance, allowing seamless transitions between RISC and VLIW execution modes without requiring mutual exclusion or pre-prepared subroutine programs.
Solution Approach 2:
The patent divides the instruction processing into distinct segments: the instruction fetch portion fetches multiple fixed-length instructions, the predecoder segment predecodes specific fields, and the program counter management portion uses this information to control PC increment. This segmentation allows RISC and VLIW processes to be merged at the instruction level rather than requiring complete process mutual exclusion.
2Productivity
If RISC processor instructions are used to start parallel execution of the VLIW control unit, then subroutine programs can be executed in parallel, but the end of execution of a given subroutine program must be awaited before the next RISC processor instruction is executed
Solution Approach 1:
By pre-decoding specific fields in the fetched instructions, the system determines VLIW execution parameters before the RISC instruction completes execution. This allows the program counter to be updated in advance for the next instruction, eliminating the need to wait for subroutine completion and enabling overlapping of RISC and VLIW execution streams.
Solution Approach 2:
The patent enables continuous useful action by allowing the program counter management portion to prepare the next program counter value during the current instruction's execution. This continuity eliminates idle waiting periods and maintains steady throughput by ensuring that instruction fetching and program counter updates can proceed without interruption.
3Productivity
If a new RISC instruction set were defined to perfectly merge with VLIW instructions, then processing efficiency would improve, but compatibility with existing software resources and development environment would be lost
Solution Approach 1:
The patent implements a universal instruction handling mechanism where the same instruction fetch portion can fetch both RISC and VLIW instructions, and the predecoder can handle specific fields in both instruction types. The program counter management portion universally applies the predecoded information regardless of instruction type, enabling efficient merged execution while maintaining compatibility with existing RISC software resources.
Solution Approach 2:
The patent applies local quality by predecoding only specific fields in instructions rather than performing complete decoding. This selective predecoding of particular fields enables the system to efficiently determine VLIW execution parameters and program counter increment values without altering the overall instruction format, thus maintaining software compatibility while achieving improved processing efficiency.
Data Source
AI summary
A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.