Processor Hardware Prefetch Control Unit Adaptation
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Solution Overview
Problem
Conventional hardware prefetch techniques face challenges in dynamically adapting to complex access patterns and are resource-intensive, with fixed timing and distance settings, which limits their effectiveness, especially in scenarios with varying stride widths and large loop unrolling.
Innovation Solution
A processor configuration that includes prefetch setting registers and a hardware prefetch control unit, allowing software to specify prefetch modes and distances, enabling flexible generation and issuance of hardware prefetch requests based on past access patterns and dynamic behavior, reducing resource consumption and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional hardware prefetch is used with fixed timing and distance settings, then circuit complexity is reduced, but adaptability to complex access patterns deteriorates
Solution Approach 1:
The patent introduces dynamic control of prefetch timing and distance through specification fields in memory access instructions. Instead of fixed hardware settings, the system allows software to dynamically specify prefetch parameters (timing, distance, granularity) based on detected access patterns, enabling adaptation to varying memory access behaviors while maintaining hardware efficiency.
Solution Approach 2:
The patent enables changing of prefetch parameters (timing, distance, granularity) by software specification in memory access instructions. This allows the system to adjust prefetch behavior dynamically according to different access patterns without requiring complex hardware reconfiguration, resolving the contradiction between fixed simple hardware and adaptable complex behavior.
2Adaptability or versatility
If software prefetch is used with explicit prefetch instructions, then flexibility in control is improved, but hardware resource consumption deteriorates
Solution Approach 1:
The patent merges software flexibility with hardware efficiency by integrating prefetch specification fields directly into memory access instructions. This combination allows software to control prefetch behavior adaptively while the hardware executes the prefetch operations efficiently in parallel, avoiding the overhead of separate prefetch instructions and reducing total hardware resource consumption.
Solution Approach 2:
The patent enables preliminary specification of prefetch parameters in memory access instructions before execution. This allows the system to prepare prefetch operations in advance with optimal parameters determined by access pattern detection, reducing the need for additional runtime hardware resources while maintaining flexible control.
3Adaptability or versatility
If hardware prefetch detects complex access patterns, then adaptability to access patterns is improved, but circuit complexity and power consumption deteriorate
Solution Approach 1:
The patent segments the prefetch control functionality into separate specification fields within memory access instructions (prefetch timing field, prefetch distance field, prefetch granularity field). This segmentation allows the hardware to implement simple fixed-time prefetch logic while software provides the complex adaptability through parameter specification, reducing hardware circuit complexity and power consumption.
Solution Approach 2:
The patent introduces specification fields in memory access instructions as intermediaries between software access pattern detection and hardware prefetch execution. These fields act as a mediator that carries prefetch parameters from software analysis to hardware implementation, enabling complex adaptability without requiring complex hardware circuitry for pattern detection and control.
4Reliability
If prefetch instructions are inserted for every cache line, then cache miss occurrence is reduced, but instruction redundancy increases
Solution Approach 1:
The patent implements partial prefetch action by introducing prefetch granularity specification that allows prefetching of only necessary data units (e.g., single cache line or multiple cache lines). This prevents excessive prefetching of redundant data while still achieving sufficient cache hit rates by prefetching only the minimal necessary amount based on access patterns.
Solution Approach 2:
The patent enables dynamic adjustment of prefetch granularity through specification fields in memory access instructions. By changing the granularity parameter, the system can optimize between prefetching individual cache lines versus larger data units, reducing instruction redundancy while maintaining high cache hit rates based on actual access patterns.
Data Source
AI summary
A processor includes an instruction executing unit which executes a memory access instruction, a cache memory unit disposed between a main memory which stores data related to the memory access instruction and the instruction executing unit, a control information retaining unit which retains control information related to a prefetch issued to the cache memory unit, an address information retaining unit which retains address information based on the memory access instruction executed in the past, and a control unit which generates and issues a hardware prefetch request. The control unit compares address information retained in the address information retaining unit and an access address in the memory access instruction executed, and generates and issues based on a comparison result a hardware prefetch request to the cache memory unit according to the control information of the control information retaining unit specified by specifying information added to the memory access instruction.