Processor Prefetch Throttling via Short Stream Counters

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Solution Overview

Problem

Overly aggressive prefetching in computer processors leads to wasted time and energy due to unused prefetched data, resulting in increased energy and bandwidth consumption.

Innovation Solution

Implementing a prefetch circuit throttling mechanism based on short stream patterns using a global short stream counter to determine the amount of throttling, reducing the number of unused prefetches and optimizing energy and bandwidth usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If prefetching is implemented to improve processor performance, then data availability for the processor is improved, but energy and bandwidth consumption increases due to overly aggressive prefetching

Engineering Contradiction:
Improveprocessor performanceVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements dynamic adjustment of prefetching behavior by introducing a throttling mechanism that modifies prefetching intensity based on detected stream patterns. The system transitions from static aggressive prefetching to dynamic adaptive prefetching, adjusting the degree of prefetching based on real-time analysis of data stream characteristics and processor usage patterns.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms by monitoring processor behavior and prefetch effectiveness, then using this information to adjust future prefetching decisions. The system analyzes stream patterns and usage information to provide feedback that controls the throttling of prefetch operations, creating a closed-loop control system that optimizes energy efficiency while maintaining performance.

Inventive Principle:
Principle #23Feedback

2Speed

If aggressive prefetching is used to ensure data availability, then data access speed is improved, but bandwidth consumption increases due to unused prefetched data

Engineering Contradiction:
Improvedata access speedVSAvoidbandwidth consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies partial action by implementing selective prefetching rather than blanket aggressive prefetching. The throttling mechanism enables the system to perform prefetching only when and where it is beneficial, based on detected stream patterns. This partial application of prefetching reduces unnecessary bandwidth consumption while maintaining data access speed for actual usage scenarios.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameters of prefetching operations by adjusting the degree of throttling based on stream pattern analysis. The system dynamically modifies prefetching parameters such as prefetch distance, quantity, and frequency based on detected data stream characteristics, thereby optimizing the balance between data access speed and bandwidth consumption.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If prefetching is increased to reduce data access delays, then processor waiting time is reduced, but energy waste increases due to unused prefetched lines

Engineering Contradiction:
Improvedata access delayVSAvoidenergy waste
Core Design Contradiction:
Loss of timeVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by performing selective prefetching based on predicted future needs rather than unconditional prefetching. The throttling mechanism enables advance preparation of data only when stream patterns indicate likely usage, reducing processor waiting time for anticipated data while avoiding energy waste on data that will not be used.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10379864B2Processor prefetch throttling based on short streams
Publication Date: 2019.08.13 INTEL CORP
  • US10379864B2 patent drawing
  • US10379864B2 patent drawing
  • US10379864B2 patent drawing

AI summary

In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.