Processor Reduction Operation Buffer for Parallel Computing
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Solution Overview
Problem
In parallel computer systems, the reduction operation is hindered by system noise due to multitasking operating systems, leading to performance deterioration during communication and computation, especially when using IO registers for accessing reduction operation devices.
Innovation Solution
A processor with a reduction operation buffer coupled to a cache coherent bus and interconnect device, allowing control information and values to be transferred directly from CPU registers to the reduction operation device without using IO registers, thereby reducing overhead and improving execution performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IO registers are used to access the reduction operation device, then the reduction operation can be performed, but system noise from multitasking operating systems causes performance deterioration
Solution Approach 1:
The patent extracts the reduction operation buffer from the general memory system and places it directly in the interconnect device, creating a dedicated pathway that isolates the reduction operation from system noise caused by multitasking operating systems. This extraction allows the reduction operation to execute independently without being affected by OS interruptions.
Solution Approach 2:
The reduction operation buffer acts as an intermediary between the processor cores and the reduction operation device. Instead of directly accessing IO registers which are susceptible to system noise, data is first placed in the buffer, which then mediates the transfer to the reduction operation device, eliminating the harmful effect of system noise on performance.
2Ease of operation
If frequent IO register access is used for reduction operations, then control can be achieved, but overhead increases and execution performance decreases
Solution Approach 1:
The patent implements preliminary action by having processor cores write control information and data values to the reduction operation buffer in advance. This preparatory step allows the reduction operation device to execute without requiring frequent interruptions for IO register access, thereby reducing execution overhead and improving performance.
Solution Approach 2:
The reduction operation buffer is designed to be self-sufficient, containing both control information and data values needed for the reduction operation. Once data is placed in the buffer, the reduction operation device can autonomously perform the operation without requiring continuous control from the processor cores through IO register access, eliminating repetitive overhead.
Data Source
AI summary
A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.