Processor Register Architecture for Thread Scheduling
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Solution Overview
Problem
Current processor designs face challenges in efficiently handling increasing communication demands with external devices, as existing methods like interrupts and polling result in delayed reaction times and high power consumption, while Field Programmable Gate Arrays (FPGAs) offer configurability but at the cost of speed, price, and energy efficiency compared to Application Specific Integrated Circuits (ASICs).
Innovation Solution
A processor architecture featuring an execution unit for multiple threads, a thread scheduler that suspends and resumes threads based on communication activity indications, and dedicated registers for each thread, allowing for flexible scheduling and power management to improve reaction time and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupts are used for handling communication activity, then the processor can respond to external devices, but the current program state must be saved before the interrupt can be acted upon, resulting in delayed reaction time
Solution Approach 1:
The processor divides communication handling into separate threads, each dedicated to specific communication sources. This segmentation allows the processor to maintain multiple execution contexts simultaneously, eliminating the need to save and restore single-program state during interrupts, thereby reducing reaction time delays
Solution Approach 2:
The processor pre-loads thread state information into dedicated register sets before communication events occur. By having thread contexts pre-prepared and accessible in hardware registers rather than memory, the processor eliminates the time penalty of saving/restoring program state during interrupt handling
2Reliability
If polling is used to check device readiness, then the processor can determine when devices are ready to supply or accept data, but the continual queries and responses introduce slow reaction time and high power consumption
Solution Approach 1:
Instead of continuous polling, the processor uses event-driven periodic action where threads are suspended and activated based on communication events. The thread scheduler activates threads only when communication activity indications occur, eliminating continuous power-consuming queries while maintaining reliable device readiness detection
Solution Approach 2:
The communication sources themselves generate activity indications that automatically trigger thread activation. This self-service mechanism eliminates the need for the processor to actively poll devices, reducing power consumption while ensuring devices notify the processor when they are ready for communication
3Adaptability or versatility
If FPGAs are used for interface controllers to achieve configurability, then the manufacturer can tailor the device to specific applications, but FPGAs are more expensive, slower and consume more power than ASICs
Solution Approach 1:
The processor implements a universal thread-based architecture that can handle multiple communication protocols and devices through software configuration rather than hardware reconfiguration. This allows a single ASIC implementation to perform multiple functions by loading different thread programs, achieving FPGA-like adaptability without the associated power consumption and cost penalties
Solution Approach 2:
The invention replaces the mechanical/reconfigurable hardware approach of FPGAs with a software-based thread scheduling system. Instead of physically reconfiguring logic circuits, the processor achieves adaptability by loading and switching between different thread programs in dedicated execution units, eliminating the power and speed penalties of FPGA reconfiguration
4Adaptability or versatility
If multiple interface controllers are provided to handle increasing communication demands, then the processor can interface with more peripheral devices, but the complexity of the system increases
Solution Approach 1:
The processor implements a universal thread-based architecture that can handle multiple communication protocols and devices through software configuration rather than hardware reconfiguration. This allows a single ASIC implementation to perform multiple functions by loading different thread programs, achieving FPGA-like adaptability without the associated power consumption and cost penalties
Solution Approach 2:
The processor divides communication handling into separate threads, each dedicated to specific communication sources. This segmentation allows the processor to maintain multiple execution contexts simultaneously, eliminating the need to save and restore single-program state during interrupts, thereby reducing reaction time delays
Data Source
Figure 1
Figure 2
Figure 2A
AI summary
The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle activity from at least one specified source. The processor also comprises a thread scheduler for scheduling a plurality of threads to be executed by the execution unit, said scheduling being based on the respective activity handled by the threads; and a plurality of sets of registers connected to the execution unit. Each set of registers is arranged to store information representing a respective one of the plurality of threads, at least a part of the information being accessible by the execution unit for use in executing the respective thread when scheduled.