Processor Device Parallel Register Bank Scheduling
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Solution Overview
Problem
Conventional processor devices lack the ability to perform high-speed processing across various arithmetic operations, particularly in deep learning applications like inference and learning processing, due to limited universal applicability and inefficiencies in parallel processing.
Innovation Solution
A processor device configuration that includes an external memory, multiple processors, register groups, a memory access unit, a control unit, and a scheduler, allowing for parallel processing by implementing the same instruction across multiple register groups with sliding addresses, and enabling each processor to access a defined bank for efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple matrix operation units are mounted to improve deep learning processing performance, then processing speed for matrix operations is improved, but the processor device lacks universal applicability to other arithmetic operations
Solution Approach 1:
The patent applies universality by designing a single processor that can execute both general arithmetic operations and matrix operations through the same instruction set. The processor performs product-sum operations (matrix operations) and other arithmetic operations without requiring specialized hardware units, achieving multi-functionality through software-controlled operation modes that adapt the same physical resources for different computational tasks.
2Productivity
If conventional parallel processing is implemented, then processing capacity is increased, but a high degree of expertise is required and data dependency between processors reduces efficiency
Solution Approach 1:
The patent applies segmentation by dividing the processing task into multiple segments that can be executed in parallel by different processors. Each processor handles a specific segment of data with its own addressing, and the system automatically manages the parallel execution and results aggregation, reducing the complexity of coordination and minimizing data dependency issues between processors.
3Speed
If data is stored in register memory accessible by multiple processors, then processing speed is improved, but the cost of high-speed register memory increases significantly
Solution Approach 1:
The patent applies local quality by providing each processor with its own dedicated register memory for storing data and instructions. This local register memory is optimized for high-speed access by that specific processor, while external memory serves as shared storage. This architecture ensures fast processing speed for each processor without requiring all processors to share expensive high-speed memory resources, thus reducing overall system cost.
Data Source
AI summary
In a processor device according to the present invention, a memory access unit reads data to be processed from an external memory and writes the data to a first register group that a plurality of processors does not access among a plurality of register groups. A control unit sequentially makes each of the plurality of processors implement a same instruction, in parallel with changing an address of a register group that stores the data to be processed. A scheduler, based on specified scenario information, specifies an instruction to be implemented and a register group to be accessed for the plurality of processors, and specifies a register group to be written to among the plurality of register groups and data to be processed that is to be written for the memory access unit.