Processor Register Bank Segmentation for Wide Packed Data
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Solution Overview
Problem
The increasing width of packed data operands in processors leads to larger register sizes and increased data movement, which can double the size of registers and register files, resulting in higher area occupancy and increased data transfer requirements during context switches and power mode transitions.
Innovation Solution
The processor allows a set of registers to be viewed or accessed as either a plurality of smaller registers or a single larger register, enabling flexible access without expanding the bit-width, thus maintaining performance with reduced area occupancy and data transfer needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of packed data operands is increased to process more data elements concurrently, then processing performance is improved, but the size of registers and register files approximately doubles
Solution Approach 1:
The register file is segmented into multiple banks (e.g., bank 0 and bank 1), where each bank contains a subset of the total registers. This segmentation allows the physical register storage to be divided into smaller, manageable units that can be accessed independently, reducing the area occupancy of any single register bank while maintaining the capability to handle wider packed data operands through coordinated access to multiple banks.
Solution Approach 2:
The patent introduces a new dimension to register organization by implementing a two-dimensional register indexing system: one dimension for the logical register number and another for the bank number. This allows the same logical register to be accessed across different banks, effectively increasing the register width capability without proportionally increasing the physical area of individual register banks.
2Productivity
If the width of packed data operands is increased to process more data elements concurrently, then processing performance is improved, but the amount of data that needs to be moved to and from registers increases
Solution Approach 1:
By segmenting the register file into multiple banks, the patent enables selective access to only the necessary register banks for each operation. When processing wide packed data, the system can access multiple smaller banks in parallel rather than moving data through a single large register, thereby reducing the total volume of data movement while maintaining high processing throughput.
3Productivity
If the size of registers is expanded to accommodate wider packed data, then more data elements can be processed in parallel, but the complexity of the register file increases
Solution Approach 1:
The register file is divided into multiple identical or similar banks, each with the same internal structure and access logic. This segmentation approach maintains uniformity across banks, simplifying the control logic and access mechanisms compared to implementing a single large, complex register. Each bank can be independently managed, reducing the overall complexity of the register file system.
Solution Approach 2:
The patent implements dynamic register banking where the association between logical registers and physical banks can change based on operational requirements. This dynamic allocation allows the system to optimize register usage patterns and reduce complexity by activating only the necessary banks for each operation, rather than maintaining fixed, complex mappings throughout.
Data Source
AI summary
A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.