Processor Register ECC for Sleep-Mode Soft Error Recovery
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Solution Overview
Problem
In low power applications, processors are susceptible to radiation-induced soft errors during sleep mode due to the lack of error checking in register words, which is not addressed by existing technologies.
Innovation Solution
Generating error-correction code for virtual arrays of physical logic registers before entering sleep mode and checking syndrome bits upon wake-up to correct any soft errors, mimicking memory error correction procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor enters low-voltage sleep mode to reduce power consumption, then energy efficiency is improved, but the risk of radiation-induced soft errors in registers increases
Solution Approach 1:
The system generates error correction codes for processor registers before entering sleep mode, similar to how memory systems prepare error checking data. This preliminary action ensures that when the processor wakes from low-voltage sleep, the pre-generated ECC data can be used to detect and correct soft errors without requiring additional error checking operations during wake-up, thus maintaining reliability while enabling power savings.
Solution Approach 2:
The invention introduces error correction code (ECC) data as an intermediary between the processor registers and potential soft errors. This ECC data acts as a mediator that can detect and correct radiation-induced errors in register contents, allowing the processor to safely operate in low-voltage sleep mode where soft errors are more likely to occur.
2Reliability
If error correction code is generated for all processor registers, then soft error correction capability is improved, but device complexity increases
Solution Approach 1:
The error correction mechanism is designed to work universally across different processor architectures and register types. By creating a virtual array representation of physical registers and applying the same ECC generation and checking methodology regardless of the specific processor type, the solution achieves broad applicability without requiring architecture-specific modifications, thus limiting the increase in device complexity.
Solution Approach 2:
The invention creates a virtual array copy of the physical register array to store error correction codes. This virtual representation allows the ECC data to be organized and managed separately from the actual register contents, simplifying the error checking process during wake-up while maintaining full error correction capability across all registers.
3Productivity
If the processor operates at deeply scaled technologies, then manufacturing efficiency is improved, but susceptibility to radiation-induced errors increases
Solution Approach 1:
The system prepares error correction codes before the processor enters vulnerable low-voltage sleep mode, cushioning against potential soft errors that may occur during this period. This beforehand protection allows deeply scaled processors to operate in sleep mode without the increased radiation sensitivity compromising reliability, enabling continued use of advanced manufacturing technologies.
Data Source
AI summary
An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.