Processor Register Monitoring for Fault Injection Detection
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Solution Overview
Problem
Existing methods to detect fault injection attacks during computer program execution are costly, complex, and require significant computational and hardware resources, making them inefficient and bulky. They often necessitate the duplication of operations performed by the processor, which is undesirable.
Innovation Solution
A method and processor configuration that utilize a monitoring module to detect fault injection attacks by verifying predefined conditions based on the current value of address registers (Program Counter and Stack Pointer) and the last executed instruction, without duplicating the execution process, using low computational and hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatial redundancy method is used to detect fault injection attacks, then detection reliability is improved, but hardware area and chip size increase
Solution Approach 1:
The patent extracts only the essential elements needed for fault detection: the fault detection unit monitors only the program counter register and instruction register, rather than duplicating entire processor components. This selective extraction maintains detection capability while minimizing hardware area occupation.
Solution Approach 2:
The patent uses simplified copying of critical register values (program counter and instruction register) into a fault detection unit, rather than creating full redundant copies of processor components. This allows comparison and detection without the area cost of complete spatial redundancy.
2Reliability
If Error Correcting Codes (ECC) are used to detect and correct faults, then fault detection capability is improved, but computational complexity and hardware area increase
Solution Approach 1:
The patent extracts only the detection function from complex error correction mechanisms, using a simple comparison-based approach in the fault detection unit. This avoids the computational overhead of ECC algorithms while maintaining fault detection capability through direct comparison of register values.
Solution Approach 2:
The patent uses lightweight, simple comparison operations in the fault detection unit rather than expensive ECC computational resources. The detection mechanism relies on basic equality checks that are computationally inexpensive compared to full error correction coding.
3Measurement precision
If detectors/sensors are added to directly detect physical fault injection, then detection accuracy is improved, but device size and cost increase
Solution Approach 1:
The patent introduces an intermediary fault detection unit that monitors the effects of fault injection on register values, rather than using physical sensors to detect the injection itself. This intermediary approach achieves detection accuracy through logical monitoring of state changes without requiring bulky physical detection hardware.
4Reliability
If cumulative signature calculation is used to detect faults, then fault detection reliability is improved, but processing resources and logical signals increase
Solution Approach 1:
The patent extracts the essential detection function from complex signature calculation mechanisms, using direct comparison of register values in the fault detection unit. This avoids the energy-intensive cumulative signature calculation while maintaining detection reliability through simple equality checks on critical registers.
5Reliability
If instruction prediction unit is added to detect faults, then fault detection capability is improved, but hardware area and processing duplication increase
Solution Approach 1:
The patent merges the fault detection function with the existing instruction execution pipeline by monitoring the program counter and instruction register values that are already present in the processor. This eliminates the need for separate prediction units while maintaining fault detection capability through integrated monitoring.
Data Source
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AI summary
The invention provides a method of detecting a fault injection attack during execution of a computer program comprising: - obtaining (201) a current value of an address register of a processor during a current clock cycle; - obtaining (202) a last executed instruction of the computer program, the last executed instruction being obtained during one of several clock cycles before the current clock cycle; - verifying (205) at least one predefined pair of conditions, each predefined pair of condition comprising a first condition related to the current value of the at least one address register and a second condition related to the last executed instruction of the computer program or to an external signal indicating an interrupt; - depending on the verification of the at least one predefined pair of conditions, detecting (210) a fault injection attack or validating (206) the last executed instruction.