Processor Register File with Dual-Function Write Port
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Solution Overview
Problem
Existing processors face performance degradation and increased circuit complexity when executing load instructions that load multiple data into multiple registers in parallel.
Innovation Solution
The processor design includes an arithmetic pipeline, a load pipeline, a selector, and a register file with dual write ports, allowing for parallel loading of data into different registers without the need for additional write ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple write ports are provided in the register file to load multiple data in parallel, then the processing performance is improved, but the circuit scale increases
Solution Approach 1:
The second write port of the register file is designed to serve dual functions: it can receive data from the arithmetic pipeline for arithmetic results, and simultaneously receive data from the load pipeline for load operations. This multi-functionality allows the register file to handle both arithmetic and load operations through the same write port, eliminating the need for additional dedicated write ports while maintaining parallel processing capability
Solution Approach 2:
A selection circuit is introduced as an intermediary component that receives data from both the arithmetic pipeline and the load pipeline, and selectively routes data to the second write port based on operation type. This mediator enables the register file to distinguish between arithmetic operations and load operations, directing data appropriately without requiring separate write ports for each function
2Productivity
If multiple pipelines are used to load multiple data in parallel, then the processing performance is improved, but the device complexity increases
Solution Approach 1:
The second write port is designed to be universal, handling both arithmetic results from the arithmetic pipeline and loaded data from the load pipeline. This multi-functional design allows the system to maintain multiple pipelines for parallel processing while avoiding the complexity increase that would result from having separate write ports for each pipeline type
3Adaptability or versatility
If the register file is provided with a number of write ports corresponding to the number of data to be loaded, then the data loading capability is improved, but the circuit scale increases
Solution Approach 1:
The second write port is designed with universal capability to receive both arithmetic results and loaded data. This versatility allows the register file to adapt to different operation types (arithmetic and load operations) without requiring additional write ports, thereby maintaining data loading capability while controlling circuit scale
Data Source
AI summary
A processor includes an arithmetic pipeline including an arithmetic unit configured to execute an arithmetic instruction and output arithmetic result data, a load pipeline configured to read first data and second data in parallel from a memory based on a first load instruction, and output the read first data and second data, a selector configured to select the second data when the second data is output from the load pipeline, and select an output of the arithmetic unit when the second data is not output from the load pipeline, and a register file including a first port configured to receive the first data from the load pipeline, a second port configured to receive data from the selector, and a plurality of registers configured to hold data received by the first port or the second port. The first data and the second data are stored in mutually different registers.