Processor Register Masking for Differential Power Analysis Protection
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Solution Overview
Problem
Differential Power Analysis (DPA) attacks exploit the characteristic power consumption of transistor logic gates in devices like smart cards, allowing attackers to determine secret information by monitoring electrical activity.
Innovation Solution
A processor design with a power consumption mask module and write module that divides registers into sections to balance bit changes, ensuring power consumption is independent of data processed by writing results in a way that masks the total number of bit changes, using a predetermined masking number to hide the writing of results across sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the result is written directly to the register without masking, then the write operation is simple and fast, but the power consumption reveals information about the data being processed
Solution Approach 1:
The register is divided into two sections: a first section for storing the actual result and a second section for storing a balancing entry. This segmentation allows the system to mask power consumption patterns by ensuring that a predetermined number of bits change across both sections during write operations, thereby preventing differential power analysis attacks while maintaining a manageable register structure.
Solution Approach 2:
A balancing entry is introduced as an intermediary element in the register write operation. This balancing entry acts as a mediator that compensates for the information leakage in power consumption. By carefully selecting the balancing entry, the system ensures that the total number of bit changes meets a predetermined threshold, thus masking the actual data being written without requiring complete redesign of the write mechanism.
2Productivity
If the number of bit changes is varied based on result size, then the write operation is efficient, but power consumption patterns leak secret information
Solution Approach 1:
The system changes the parameter of bit change count from being variable (based on result size) to being fixed (predetermined masking number). By enforcing a predetermined number of bit changes regardless of the actual result size, the power consumption pattern becomes uniform and predictable, eliminating the leakage of secret information while still allowing efficient write operations through the balancing entry mechanism.
3Reliability
If masking entries are added to balance bit changes, then power consumption is masked, but the register update complexity increases
Solution Approach 1:
The register is divided into two sections: a first section for storing the actual result and a second section for storing a balancing entry. This segmentation allows the system to mask power consumption patterns by ensuring that a predetermined number of bits change across both sections during write operations, thereby preventing differential power analysis attacks while maintaining a manageable register structure.
Solution Approach 2:
Instead of completely redesigning the register update process, the system creates a simplified copy or model of the update mechanism that operates on the balanced bit change principle. The balancing entry serves as a template that can be systematically applied to mask power consumption without requiring complex dynamic calculations during each write operation.
Data Source
AI summary
A device including a processor to perform an operation yielding a result, the processor including a register including bit storage elements and including a first and second section, each element being operative to store a bit value, and a power consumption mask module to determine whether the whole result can be completely written in half or less than half of the register, determine a balancing entry if the result can be completely written in half or less than half of the register, a write module to perform a single write operation to the register including writing the result and the balancing entry to the first and second section, respectively, if the result can be completely written in half or less than half of the register else writing the result of the operation across at least part of the first and second section. Related apparatus and methods are also described.