Processor Register Remapping for Scalar Vector Alignment
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Solution Overview
Problem
The existing register mapping architectures, such as those in ARM AArch32 and AArch64, face challenges in aligning 32 or 64-bit FP registers within 128-bit wide registers, leading to misalignment issues during scalar and vector operations, necessitating a solution to support both execution modes effectively.
Innovation Solution
A system and method for remapping registers based on a change in execution mode, where a sequence of instructions identifies a shift from one register mapping to another, allowing data reorganization within the processor to align registers appropriately for either scalar or vector operations, preserving data and optimizing register usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 32 or 64 bit FP registers are packed into a 128-bit wide register to increase the number of registers, then the quantity of registers is improved, but the alignment precision deteriorates because the smaller FP registers cannot be aligned as needed for scalar operations
Solution Approach 1:
The patent implements dynamic register remapping that adapts the register layout based on the execution mode (scalar or vector). The system switches between different register mappings: a first mapping for scalar operations and a second mapping for vector operations. This dynamic adaptation allows the same physical register structure to provide different alignment characteristics as needed, resolving the contradiction between having many registers and maintaining proper alignment.
Solution Approach 2:
The patent changes the register mapping parameters based on the operation type. When transitioning from scalar to vector mode, the system remaps registers to change their alignment properties. This parameter change enables the register file to present different effective layouts (32-bit aligned for scalar, 128-bit aligned for vector) from the same physical structure, simultaneously satisfying both alignment requirements.
2Adaptability or versatility
If two different register representations (32-bit aligned and 128-bit aligned) are provided to support both AArch64 and AArch32 architectures, then the adaptability is improved, but the device complexity increases because both representations are not suitable for both scalar and vector operations
Solution Approach 1:
The patent makes a single register file universal by implementing multiple register mappings that can be activated based on the execution mode. Instead of maintaining separate register files for different architectures, the system uses one physical register file that can be virtually remapped to present different alignment characteristics. This multi-functional approach supports both AArch64 and AArch32 architectures while avoiding the complexity of duplicate register structures.
Solution Approach 2:
The patent introduces a register remapping mechanism as an intermediary layer between the physical register file and the architectural register interface. This intermediary component translates between different register mappings (AArch32 and AArch64) without requiring separate physical register files. The remapper acts as a mediator that handles the complexity of architectural compatibility while presenting a unified physical structure.
3Manufacturing precision
If data reorganization is performed to align registers for scalar operations, then the alignment precision is improved, but the loss of time increases due to the reorganization overhead when switching execution modes
Solution Approach 1:
The patent performs preliminary actions by pre-defining multiple register mappings (first mapping for scalar mode, second mapping for vector mode) that can be quickly switched between. Instead of performing reorganization from scratch each time, the system has pre-prepared the necessary mapping configurations and can transition between them efficiently, reducing the time penalty for mode changes.
Solution Approach 2:
The patent uses copying mechanisms to efficiently transition between register mappings. Rather than physically moving all data, the system can copy or point to different mapping configurations. This allows rapid switching between scalar and vector modes by copying the appropriate mapping metadata while preserving the actual register data, significantly reducing transition time.
Data Source
AI summary
A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.