Processor Register Comparison for Soft Error Detection
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Solution Overview
Problem
Existing processors face challenges in accurately detecting soft errors caused by transient faults, such as bit value reversals due to neutron or alpha particle collisions, which can lead to fatal processing errors without efficient detection mechanisms.
Innovation Solution
A processor design that includes an instruction pipeline with an original and duplicate instruction processing system, utilizing original and duplicate register files and a comparing unit to detect soft errors by comparing results across these registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a duplicate instruction processing system with original and duplicate register files is implemented, then soft error detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent creates a duplicate copy of the instruction processing pipeline, including duplicate instruction registers, duplicate register files, and duplicate execution units. This copy processes the same original instruction independently, and the results from both the original and duplicate pipelines are compared to detect soft errors. The copying approach enables error detection without requiring complete redundancy of the entire processor system.
Solution Approach 2:
The patent applies error detection resources selectively to critical components where soft errors have the most impact. Instead of duplicating the entire processor, the duplicate register files and comparing units are strategically placed at specific locations in the instruction pipeline where error detection provides maximum benefit while minimizing overall system complexity.
2Reliability
If duplicate register files and comparing units are added for soft error detection, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent performs error detection during the normal instruction execution process by comparing results as they are being produced in the pipeline, rather than requiring separate verification steps. The comparing units operate concurrently with instruction execution, detecting errors in real-time without adding significant energy overhead to the processing workflow.
3Reliability
If duplicate instruction processing is implemented sequentially in the instruction pipeline, then soft error detection capability is improved, but productivity decreases
Solution Approach 1:
The patent maintains continuous instruction processing by implementing the duplicate pipeline operations concurrently with the original pipeline rather than sequentially. Both the original and duplicate instructions are processed in parallel through separate execution paths, with results compared at the appropriate pipeline stage, ensuring that error detection does not interrupt the continuous flow of instruction execution.
Data Source
AI summary
A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nth index thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nth index thereof. A comparing unit compares the register of the nth index in the original register file with the register of nth index in the duplicate register file and outputs an error detection signal, in response to a control signal.