Processor Reservation Station Speculative Execution Control
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Solution Overview
Problem
The restriction of speculative execution in processing apparatuses to counter security vulnerabilities like Spectre leads to significant performance deterioration, as it prevents unauthorized memory access but also hampers legitimate operations.
Innovation Solution
A processing apparatus with a reservation station that distinguishes between operation and memory access instructions, restricting speculative execution only for memory access instructions, ensuring that speculative memory access is canceled before it leaves a trace in the data cache, thereby preventing data leakage while allowing other instructions to execute speculatively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If speculative execution is restricted to block security attacks, then security is improved, but processing performance deteriorates significantly
Solution Approach 1:
The patent segments the speculative execution control into two parts: operation instructions are allowed to execute speculatively while memory access instructions are restricted from speculative execution. This segmentation resolves the contradiction by permitting performance-critical operations to run speculatively while blocking security-vulnerable memory accesses.
Solution Approach 2:
The patent applies different execution policies to different instruction types locally. Operation instructions receive speculative execution permission to maintain performance, while memory access instructions are denied speculative execution to ensure security. This local differentiation resolves the global contradiction between security and performance.
2Object-affected harmful factors
If speculative execution is completely blocked, then unauthorized memory access is prevented, but legitimate processing operations are also hampered
Solution Approach 1:
The patent divides instructions into operation instructions and memory access instructions, applying different speculative execution policies to each segment. This allows legitimate processing operations to proceed speculatively while blocking unauthorized memory access attempts.
Solution Approach 2:
The patent introduces an intermediary mechanism (the instruction type detection and control logic) that mediates between speculative execution requests and security requirements. This intermediary allows benign operations while blocking harmful memory accesses.
Data Source
AI summary
A processing apparatus includes a processor. The processor stores a plurality of instruction codes, each of the plurality of instruction codes is a result of decoding of an instruction, selects an instruction code that is ready to be input from the stored instruction codes, when the selected instruction code is an operation instruction, uses for the processing, a register for processing corresponding to a write destination of the operation instruction, after detecting that operands to be used for the processing are ready, in the next cycle, issues a subsequent instruction, and when the selected instruction code is a memory access instruction, uses for the address calculation, the register, writes a processing result and load data that have been temporarily written in a buffer for register update from the buffer to the register at the time of instruction completion, after the completion of the memory access instruction, issues a subsequent instruction.