Data Processor Reset Management via Checksum and Flag Logic

The patent segments the reset mechanism into distinct types by introducing separate reset sources: watchdog timer resets and software instruction resets. This is achieved by dividing the reset functionality into independent pathways - one triggered by watchdog timer events and another by dedicated software instructions (such as RFW - Reset From Software). Each reset type can be independently controlled and identified through separate flags (WDOG_RESET_FLAG and SOFTWARE_RESET_FLAG), allowing flexible selection of reset causes without increasing overall system complexity.

The patent introduces intermediary elements to manage the complexity of multiple reset sources. These include separate flag registers (WDOG_RESET_FLAG, SOFTWARE_RESET_FLAG) that act as intermediaries between different reset sources and the system state. Additionally, a reset cause identification mechanism serves as an intermediary that translates multiple possible reset sources into distinguishable states, enabling the system to handle complex reset scenarios through structured intermediate representations rather than direct complex interactions.

The patent implements universal reset management by creating a multi-functional reset system that handles both traditional watchdog resets and new software-initiated resets through a unified framework. The reset mechanism is designed to serve multiple purposes: fault recovery via watchdog, controlled restarts via software instructions, and intermediate states (such as interrupt-only or register-reset-only modes). This universal approach allows the same hardware infrastructure to support diverse reset scenarios without requiring separate dedicated circuits for each function.

The patent employs parameter changes to enable flexible reset behavior without altering the fundamental processor architecture. By introducing configurable parameters such as reset mode selections (full reset, interrupt only, register reset only), timeout values, and flag states, the system achieves customizable reset operations through software-controlled parameters rather than hardware modifications. This allows the same physical architecture to exhibit different functional behaviors based on parameter settings.