Processor Reset Hold Controller for Stable Memory Transition
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Solution Overview
Problem
Processor systems face instability when transitioning from a reset state to an active state, particularly when non-volatile memory is being programmed, leading to potential system deadlocks due to erroneous behavior from fetching code from unstable memory states.
Innovation Solution
A bifurcated processor-chip reset control architecture that includes a pad interface for external debug and reset signals, a controller to detect and generate a hold signal after the external reset has ceased, allowing the processor to maintain a reset state until a clear request is sent, enabling external access and ensuring stable transition to an active state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor transitions immediately to an active state after the external reset signal is discontinued, then the system responds quickly to reset release, but the processor may fetch code from unstable non-volatile memory states causing system deadlocks
Solution Approach 1:
The controller generates a hold signal that extends the reset state beyond the external reset signal duration. This preliminary action ensures that the processor remains in a stable reset state until the non-volatile memory is fully programmed and stable, preventing any attempt to fetch code from unstable memory states. The hold signal acts as a protective measure taken in advance to avoid system deadlocks.
2Reliability
If the processor is held in reset state after external reset signal discontinuation, then memory programming stability is ensured, but the processor cannot execute code or respond to system manager requests
Solution Approach 1:
The system dynamically transitions the processor through different states based on system conditions. The processor is held in reset state during memory programming to ensure stability, then automatically transitions to an active state once the hold signal discontinues. This dynamic state management allows the system to optimize between reliability during programming and productivity during normal operation.
Solution Approach 2:
The controller monitors the programming status of non-volatile memory and uses this feedback to control the hold signal duration. When programming is complete and memory is stable, the controller discontinues the hold signal, allowing the processor to transition to the active state. This feedback mechanism ensures the processor only executes code when memory is in a stable, reliable state.
3Reliability
If a hold signal is generated to maintain processor reset state, then system deadlock is prevented, but additional control circuitry and signal management are required
Solution Approach 1:
The controller performs multiple functions: it detects the external reset signal, generates the hold signal to extend the reset state, monitors programming completion, and discontinues the hold signal when appropriate. By consolidating these functions in a single controller, the design achieves reliable deadlock prevention without proportionally increasing system complexity.
Data Source
AI summary
Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.