Processor Resetting Multiple Registers in Single Cycle
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Solution Overview
Problem
Current processor architectures lack efficient instructions for resetting multiple registers, leading to latency issues during task switching and system calls, particularly in multi-tasking and event-driven applications like network devices.
Innovation Solution
Incorporating specific instructions, such as ZALLBUTONE, ZCALLER, and ZCALLEE, into the processor's ISA that allow for the resetting of all registers except one, caller-saved registers, or callee-saved registers in a single clock cycle, reducing latency in system calls and task switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional processor architectures are used without multiple register reset instructions, then the processor can maintain a simpler instruction set, but task switching and system calls experience increased latency due to multiple individual reset operations
Solution Approach 1:
The patent combines multiple individual register reset operations into a single instruction (reset multiple registers instruction) that can reset multiple registers simultaneously in one clock cycle. This merging of operations directly reduces task switching latency while the instruction set complexity increase is minimal since only one new instruction type is added.
Solution Approach 2:
The reset multiple registers instruction provides multi-functionality by enabling different reset scenarios (task switching, system calls, exception handling) through a single universal instruction. The instruction can operate on different register sets (all registers, caller-saved registers, callee-saved registers) making it adaptable to various processing needs without requiring multiple specialized instructions.
2Productivity
If multiple individual reset operations are used for each register, then the instruction set remains simple, but system call performance deteriorates due to cumulative execution time
Solution Approach 1:
The patent merges multiple sequential register reset operations into a single parallel operation executed in one clock cycle. This eliminates the cumulative execution time of individual reset instructions while maintaining simple implementation through a single new instruction type.
Solution Approach 2:
The processor core is designed with preliminary action built-in by having the reset multiple registers instruction pre-configured to identify and reset multiple registers simultaneously. The instruction encoding includes register mask fields that pre-specify which registers should be reset, eliminating the need for sequential identification and resetting during execution.
3Reliability
If all registers are reset during task switching, then information leakage is prevented, but unnecessary reset operations increase execution time
Solution Approach 1:
The patent applies local quality by enabling selective resetting of specific register sets (caller-saved, callee-saved, or all registers) based on the specific task switching context. The reset multiple registers instruction includes mask fields that allow precise control over which registers are reset, ensuring information security for critical registers while avoiding unnecessary reset operations on registers that maintain their values.
Solution Approach 2:
The patent implements partial action by resetting only the necessary subset of registers required for secure task switching rather than always resetting all registers. The instruction can be configured to reset only caller-saved registers or only callee-saved registers when full reset is not needed, reducing execution time while maintaining security.
Data Source
AI summary
A processor includes a set of registers and a processing core. The processing core is configured to execute instructions, including an instruction that causes the core to reset a plurality of the registers in the set.