Processor Reset Controller Voltage Overshoot Prevention
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Solution Overview
Problem
The existing reset schemes in microcontrollers can cause voltage overshoot due to sudden changes in clock frequency and switching activity, leading to more severe reset events and making it difficult for software to determine the original cause of the reset, especially in smaller technologies with multiple cores.
Innovation Solution
A method involving a reset controller that delays the forwarding of reset signals and gradually reduces clock frequency to prevent voltage overshoot, using a combination of a frequency adapter and isolation units to manage the reset sequence and maintain chip functionality during the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a reset signal is immediately forwarded to processor parts, then the reset response time is fast, but voltage overshoot occurs due to sudden drop in switching activity
Solution Approach 1:
The reset controller delays forwarding the reset signal to processor parts for a predetermined period before actually asserting reset. This preliminary delay allows the system to prepare for the reset event, preventing sudden switching activity drops that cause voltage overshoot, while still maintaining fast reset response overall.
Solution Approach 2:
The system dynamically adjusts the reset timing based on system state. The reset controller monitors processor activity and selectively delays reset signals based on current operating conditions, optimizing between fast reset response and voltage stability in real-time.
2Productivity
If clock frequency is suddenly reduced or stopped during reset, then processor parts are quickly reset, but voltage overshoot beyond operational range occurs
Solution Approach 1:
The system performs preliminary frequency reduction before asserting reset. The reset controller gradually reduces clock frequency to a lower level before stopping it, allowing voltage to stabilize and preventing overshoot that would occur with sudden frequency changes.
Solution Approach 2:
The clock frequency is reduced in periodic steps rather than suddenly. The system applies multiple frequency reduction phases with intermediate stabilization periods, ensuring voltage remains within operational range throughout the reset process.
3Reliability
If a severe level of reset is triggered by voltage overshoot, then voltage stability is enforced, but the original cause of reset cannot be determined
Solution Approach 1:
The reset controller acts as an intermediary between the reset trigger and processor parts. It captures and stores information about the original reset cause before preventing voltage overshoot, ensuring that diagnostic information is preserved even as voltage stability is enforced.
Solution Approach 2:
The system performs preliminary capture of reset cause information before the reset sequence begins. By recording the original trigger event in advance, the system ensures diagnostic data is preserved even if subsequent reset events occur during the reset process.
Data Source
AI summary
The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts of said processor need to be reset, and forwarding of said reset signal to said parts to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts to be reset. The clock frequency of at least one of the parts to be reset is gradually decreased during said period of time. In this way the total activity of the processor device is gradually decreased so as to avoid an on-chip voltage overshoot, which could cause a total reset of all the parts of the processor.