Processor Synchronization via Instruction Retirement Counters
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Solution Overview
Problem
Emerging non-deterministic processor execution models complicate fault tolerance in computer systems, as multiple processors executing the same software may not perform instructions in the same order or number, making strict and loose lock-step fault tolerance methods impractical.
Innovation Solution
A computing system with multiple processors executes duplicate copies of user programs in a logical processor, using synchronization logic to consolidate and compare read/write requests, handle interrupts, and provide consistent time of day information, allowing for loosely lock-stepped execution and fault tolerance without strict cycle-by-cycle synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict lock-step synchronization is implemented to ensure fault tolerance, then reliability is improved, but device complexity and difficulty of implementation increase due to phase differences in clocking signals and larger die sizes
Solution Approach 1:
The patent extracts the synchronization requirement from the clocking signal domain and relocates it to the instruction completion domain. By using retirement counters and synchronization barriers at instruction retirement points rather than enforcing cycle-by-cycle clock synchronization, the system achieves fault tolerance without requiring precise clock phase alignment across processors.
Solution Approach 2:
The patent changes the synchronization parameter from temporal (cycle-by-cycle timing) to instructional (retirement count). Instead of synchronizing based on clock cycles and wall clock time, the system synchronizes based on the number of instructions retired, allowing processors to execute at different speeds while maintaining fault tolerance through counter-based synchronization.
2Productivity
If non-deterministic processor execution features such as speculative execution and out of order processing are used to improve performance, then productivity is improved, but strict lock-step and loose lock-step fault tolerance methods become inapplicable
Solution Approach 1:
The patent segments the instruction execution process into distinct phases: instruction fetch, execution, and retirement. Fault tolerance is implemented at the retirement phase through synchronization barriers, while the fetch and execution phases can proceed non-deterministically with speculative execution and out-of-order processing. This segmentation allows performance features to operate freely while maintaining reliability at critical synchronization points.
Solution Approach 2:
The patent introduces retirement counters and synchronization barriers as intermediary mechanisms between non-deterministic execution and fault tolerance requirements. These intermediaries track instruction retirement status and coordinate synchronization without constraining the underlying execution model, allowing speculative execution and out-of-order processing to coexist with reliability mechanisms.
3Ease of operation
If processors are allowed to execute instructions at different rates without synchronization, then ease of operation is improved, but reliability deteriorates as processors may get too far removed from one another
Solution Approach 1:
The patent implements periodic synchronization at instruction retirement intervals rather than continuous cycle-by-cycle synchronization. Retirement counters increment with each retired instruction and trigger synchronization barriers at predetermined intervals, allowing processors to operate independently between synchronization points while periodically re-establishing coordination to prevent excessive divergence.
Data Source
AI summary
A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.