Processor Hardware ROP JOP Attack Protection via Address Signing
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Solution Overview
Problem
Return-Oriented Programming (ROP) and Jump Oriented Programming (JOP) attacks compromise system security by modifying return or jump addresses, disrupting execution flow and leading to privilege escalation, which existing technologies fail to effectively prevent.
Innovation Solution
A processor with hardware circuitry that detects modifications to return or jump addresses by signing and authenticating them using cryptographic operations, initiating error handling if authentication fails to prevent execution at modified addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional address verification methods are used, then device complexity is low, but system security against ROP/JOP attacks is insufficient
Solution Approach 1:
The processor performs preliminary cryptographic signing of return addresses and jump targets when they are written to memory, and preliminarily authenticates them before execution. This advance preparation ensures that only valid addresses can be executed, preventing ROP/JOP attacks while maintaining a manageable level of complexity through integrated hardware support
Solution Approach 2:
Cryptographic signatures act as an intermediary mechanism between address storage and address execution. The signature verification process serves as a mediator that validates address integrity without requiring complex software-based checks, thus improving security while keeping the added complexity minimal through hardware implementation
2Reliability
If cryptographic signing and verification is implemented, then address integrity is ensured, but processing time increases
Solution Approach 1:
Cryptographic signing is performed preliminarily when addresses are first written to memory, so that the computationally intensive operation is completed in advance rather than at execution time. This allows the verification stage to be faster, minimizing the time loss during critical execution paths while ensuring address integrity
Solution Approach 2:
The patent replaces software-based address verification mechanisms with hardware-implemented cryptographic operations. This substitution significantly reduces processing time by performing signing and verification in parallel with other operations and utilizing dedicated hardware circuits, thus ensuring address integrity with minimal time penalty
Data Source
AI summary
In an embodiment, a processor includes hardware circuitry and/or supports instructions which may be used to detect that a return address or jump address has been modified since it was written to memory. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified address. In an embodiment, the processor may perform a cryptographic sign operation on the return address/jump address before writing the signed return address/jump address to memory and the signature may be verified before the address is used as a return target or jump target. Security of the system may be improved by foiling ROP/JOP attacks.