Processor Routing Bus Dynamic Domain Configuration
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Solution Overview
Problem
Current computer networks face challenges in maximizing link utilization, particularly in machine learning and artificial intelligence applications, where data exchange between processors is often suboptimal, leading to underutilization of processing capacity and power.
Innovation Solution
A processor architecture with multiple processing units, on-chip interconnects, external interfaces, and a routing bus that enables efficient packet routing between processors, allowing for flexible routing domains across multiple chassis and optimizing data exchange through a network of interconnected processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data exchange between processors is performed using conventional routing methods, then network connectivity is maintained, but link utilization is suboptimal and bandwidth is underutilized
Solution Approach 1:
The routing register dynamically configures the routing domain for each processor based on its physical location in the network topology. This dynamic configuration enables the routing behavior to adapt to the network structure, allowing packets to be routed through optimal paths that maximize link utilization and bandwidth efficiency.
Solution Approach 2:
The patent changes the routing parameter (routing domain) based on the processor's physical location. By modifying the routing register contents according to position, the system optimizes data exchange paths to utilize available bandwidth more effectively, transforming static routing into location-aware dynamic routing.
2Adaptability or versatility
If the routing domain is restricted to a single chassis, then routing configuration is simplified, but network flexibility and accessibility across multiple chassis are limited
Solution Approach 1:
The routing domain is segmented into location-specific configurations, where each processor has a routing register tailored to its physical position in the network. This segmentation allows each processor to have optimized routing behavior for its specific location while maintaining overall network flexibility and enabling cross-chassis communication.
3Ease of manufacture
If vertices are compiled with constraints on specific tiles and IPUs, then compilation control is improved, but the constraints limit the flexibility of data exchange optimization
Solution Approach 1:
The routing domain is dynamically determined based on the processor's physical location rather than being statically constrained during compilation. This dynamic approach allows the system to automatically optimize data exchange paths without imposing restrictive compilation constraints, thereby improving both ease of manufacture and data exchange productivity.
Data Source
AI summary
A processor in a network has a plurality of processing units arranged on a chip. An on-chip interconnect enables data to be exchanged between the processing units. A plurality of external interfaces are configured to communicate data off chip in the form of packets, each packet having a destination address identifying a destination of the packet. The external interfaces are connected to respective additional connected processors. A routing bus routes packets between the processing units and the external interfaces. A routing register defines a routing domain for the processor, the routing domain comprising one or more of the additional processor, and at least a subset of further additional processors of the network, wherein the additional processors of the subset are directly or indirectly connected to the processor. The routing domain can be modified by changing the contents of the routing register as a sliding window domain.