Reconfigurable Processor Routing Cost Estimation for Bandwidth Allocation
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Solution Overview
Problem
Traditional compilers struggle to optimize the performance of highly-parallel applications on reconfigurable processors like CGRAs, as they lack the ability to accurately estimate the cost of implementing applications during placement and routing, leading to inefficient utilization of hardware resources.
Innovation Solution
A cost estimation tool is developed to estimate the realized bandwidth consumption of logical edges between producer and consumer units in operation unit graphs during placement and routing on reconfigurable processors, guiding the compiler to optimize hardware resource allocation and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional compilers are used for placement and routing on reconfigurable processors, then the implementation process is simple, but the performance optimization is insufficient due to inability to accurately estimate bandwidth consumption
Solution Approach 1:
The cost estimation tool performs preliminary estimation of bandwidth consumption during the compilation phase, before actual placement and routing execution. This allows the compiler to predict resource requirements and optimize the implementation plan in advance, achieving accurate measurement without adding significant runtime complexity.
Solution Approach 2:
A cost estimation tool is introduced as an intermediary component between the traditional compiler and the placement/routing process. This mediator provides accurate bandwidth consumption estimates by analyzing the operation unit graph and logical edge connections, enabling performance optimization without fundamentally redesigning the entire compilation system.
2Productivity
If hardware resources are allocated without cost estimation, then the allocation process is fast, but the hardware utilization efficiency is low
Solution Approach 1:
The cost estimation tool performs resource requirement analysis during the compilation phase, before actual hardware allocation. This preliminary action provides accurate bandwidth consumption data that guides efficient resource allocation, improving hardware utilization without significantly extending the overall deployment time.
Solution Approach 2:
The cost estimation tool provides feedback information about bandwidth consumption and resource requirements to the placement and routing process. This feedback mechanism enables the compiler to make informed decisions about resource allocation, optimizing hardware utilization while maintaining efficient computation through iterative refinement.
3Manufacturing precision
If detailed cost estimation is performed for each logical edge, then the resource allocation accuracy is high, but the computational overhead increases
Solution Approach 1:
The cost estimation process is segmented by focusing on individual logical edges within the operation unit graph. Each logical edge's bandwidth consumption is estimated independently based on its specific characteristics, allowing precise resource allocation without requiring exhaustive analysis of the entire system at once, thus reducing overall computational overhead.
Data Source
AI summary
The present application describes a system with a routing cost estimation tool for routing a logical edge between a logical producer unit and a logical consumer unit onto a reconfigurable processor and a method of operating such a routing cost estimation tool. The method comprises receiving a tentative assignment of the logical producer unit, the logical consumer unit, and the logical edge onto a physical producer unit, a physical consumer unit, and a physical link of the reconfigurable processor, respectively, determining a number of active cycles of the logical edge; determining a number of stage cycles, determining a scaling factor of a realized bandwidth based on a division of the number of active cycles by the number of stage cycles, and determining a realized bandwidth consumption of the tentative assignment based on the scaling factor of the realized bandwidth.