Application Processor Scan Architecture for Internal Debug Data Capture
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Solution Overview
Problem
The increasing integration density of semiconductor chips makes it time-consuming and resource-intensive to test them effectively, with existing Design For Testability (DFT) techniques, such as scan tests, requiring external apparatuses to gather and store debugging data.
Innovation Solution
An integrated circuit (IC) with built-in scanner and memory controllers that gather and store debugging data internally, allowing for error detection and correction without external devices, by using test logic and scan chains to collect and store scan data in a memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan test technique is used to debug hardware and software errors, then error detection capability is improved, but testing time and resource consumption increase significantly
Solution Approach 1:
The patent implements preliminary action by pre-configuring scan chains and test logic within the SoC before actual operation. The scan test mechanism is built-in and ready to capture debugging data immediately when errors occur, eliminating the need for external apparatus setup and reducing testing time while maintaining error detection capability
2Reliability
If external apparatus is used to gather and store debugging data, then debugging functionality is achieved, but device complexity and resource requirements increase
Solution Approach 1:
The patent merges the debugging functionality directly into the SoC by integrating scan chains, test logic, and memory controllers within the chip itself. This consolidation eliminates the need for external debugging apparatus, reduces device complexity, and enables self-contained error detection and data storage capabilities
Solution Approach 2:
The SoC performs debugging operations autonomously using its built-in scan test mechanism. The system can independently gather debugging data from internal components, store it in allocated memory, and maintain operation continuity without requiring external apparatus intervention,从而实现 self-service debugging functionality
3Productivity
If integration density of semiconductor chips is increased, then chip functionality and performance are improved, but testing and debugging become more time-consuming and resource-intensive
Solution Approach 1:
The patent applies segmentation by dividing the SoC into multiple functional blocks, each with its own dedicated scan chain and test logic. This modular approach allows for targeted testing of specific segments rather than requiring comprehensive testing of the entire high-density chip, thereby reducing testing time while maintaining the ability to debug complex integrated circuits
Data Source
AI summary
An integrated circuit (IC) includes a plurality of intellectual properties (IPs), each of the plurality of IPs includes a test logic. A first memory controller provides user data received from at least one of the plurality of IPs to a first memory in a first operation mode. A scanner gathers debugging data from the test logics of the plurality of IPs in a second operation mode. And a second memory controller receives the debugging data from the scanner and provides the debugging data to the first memory in the second operation mode.