Processor Scheduler for Interruptible Instruction Batches
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Solution Overview
Problem
Conventional processor architectures are unable to issue and execute batches of instructions while allowing for interruptions, which is necessary for handling interrupt routines and other operational requirements.
Innovation Solution
A scheduler unit is configured to enable interruption of batches of instructions by prioritizing interrupt routines and storing batch-level resources in memory to resume execution after the interrupt routine has finished, allowing for efficient power management and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are issued one at a time with conventional scheduling, then interrupt handling is straightforward, but execution efficiency is reduced due to spread-out latency and frequent scheduler execution
Solution Approach 1:
The patent segments the instruction batch into individual instructions that can be dispatched separately to functional units, while maintaining batch-level resource allocation. This allows the scheduler to issue multiple instructions in a batch manner for efficiency while still enabling individual instruction interruption and handling, thus resolving the contradiction between execution efficiency and interrupt handling capability.
Solution Approach 2:
The patent performs preliminary actions by pre-allocating batch-level resources (such as register file portions) for the entire batch of instructions before execution begins. This preliminary resource allocation enables the batch to be executed with improved efficiency while maintaining the ability to interrupt and handle individual instructions, as the resources are already reserved and can be quickly released or reallocated upon interruption.
2Loss of energy
If batch instructions are issued for power savings, then fewer clock cycles are needed, but interrupt capability is lost
Solution Approach 1:
The patent introduces dynamic control mechanisms that allow the processor to switch between batch execution mode and individual instruction mode based on interrupt requirements. The scheduler can dynamically allocate and release batch-level resources, and functional units can dynamically transition between processing batch instructions and handling interrupts, thus maintaining both power efficiency and interrupt capability.
Solution Approach 2:
The patent changes the operational parameters of the processor by allowing the batch size and resource allocation to be adjusted based on interrupt likelihood and system state. When interrupts are expected, the batch size can be reduced or resources can be allocated more conservatively, while when interrupts are less likely, larger batches can be issued for maximum power savings, thus balancing energy efficiency with interrupt capability.
3Reliability
If batch-level resources are allocated for interrupt handling, then interrupt routines can be serviced, but resource availability for batch execution is reduced
Solution Approach 1:
The patent implements periodic resource allocation where batch-level resources are allocated to the batch for the duration of its execution, and only temporarily diverted to interrupt handling when an interrupt occurs. The resources are then periodically returned to the batch after interrupt service completion, allowing reliable interrupt handling while minimizing impact on batch execution throughput during normal operation.
Solution Approach 2:
The patent creates copies of batch-level resources (such as register file portions or buffer allocations) that can be used for both batch execution and interrupt handling. When an interrupt occurs, the system can switch to using the copied resources for the interrupt routine while preserving the original batch resources, thus maintaining interrupt handling reliability without permanently reducing resource availability for batch execution.
Data Source
AI summary
A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.