Multi-thread Processor Scheduler Rescheduling Nondispatchable Threads

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Solution Overview

Problem

In multi-thread processors, existing scheduling techniques such as round robin and priority systems struggle to ensure flexible execution times for hardware threads, leading to inefficiencies like reduced processing efficiency and inability to maintain designed execution ratios due to nondispatchable threads, especially when I/O waiting occurs.

Innovation Solution

A scheduler that reschedules hardware threads by repeatedly specifying threads from a first group and an arbitrary thread from a second group, ensuring execution ratios are maintained by replacing nondispatchable threads with dispatchable ones from the second group.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a round robin scheduling system is used to ensure fair execution time allocation, then each hardware thread receives equal execution opportunities, but the execution time of high priority threads cannot be sufficiently guaranteed when there are many threads

Engineering Contradiction:
Improvefair execution time allocationVSAvoidexecution time of high priority threads
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The scheduling system is segmented into two distinct queues: a first queue for high priority hardware threads and a second queue for other hardware threads. This segmentation allows the scheduler to differentiate between threads based on priority, ensuring that high priority threads receive sufficient execution time while still maintaining fair allocation for other threads through the round robin mechanism within each queue.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a priority scheduling system is used to ensure high priority threads execute first, then high priority threads receive sufficient execution time, but low priority threads cannot be processed when high priority threads continue processing

Engineering Contradiction:
Improveexecution time of high priority threadsVSAvoidprocessing of low priority threads
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The scheduling system is segmented into two distinct queues: a first queue for high priority hardware threads and a second queue for other hardware threads. This segmentation allows the scheduler to differentiate between threads based on priority, ensuring that high priority threads receive sufficient execution time while still maintaining fair allocation for other threads through the round robin mechanism within each queue.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scheduler performs periodic switching between the first queue and the second queue in a cyclic manner. After completing a round of scheduling in the first queue, the scheduler transitions to the second queue to process low priority threads, then returns to the first queue. This periodic action ensures that both high and low priority threads receive execution opportunities, preventing starvation of lower priority threads while maintaining priority-based scheduling.

Inventive Principle:
Principle #19Periodic action

3Stability of the object's composition

If fixed execution periods are used to maintain execution ratios between thread groups, then execution ratios are maintained, but processing efficiency decreases when threads become nondispatchable

Engineering Contradiction:
Improveexecution ratio between thread groupsVSAvoidprocessing efficiency
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The scheduling system dynamically adapts when threads become nondispatchable. When a thread in the first queue becomes nondispatchable, the scheduler detects this state and substitutes another thread from the first queue to maintain the execution ratio. This dynamic adjustment allows the system to maintain stable execution ratios between thread groups while preventing performance degradation by actively responding to changes in thread dispatchability status.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The scheduler implements feedback mechanisms to monitor the dispatchability status of hardware threads. When a thread becomes nondispatchable, the scheduler receives feedback about this state and automatically adjusts the scheduling by substituting another thread from the same queue. This feedback loop ensures that execution ratios are maintained while processing efficiency is preserved through automatic correction of scheduling issues.

Inventive Principle:
Principle #23Feedback

4Adaptability or versatility

If arbitrary threads are scheduled in the second execution period to adapt to processing situations, then scheduling flexibility is improved, but execution ratios between thread groups cannot be maintained

Engineering Contradiction:
Improvescheduling flexibilityVSAvoidexecution ratio between thread groups
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The scheduler performs periodic switching between the first queue and the second queue in a cyclic manner. After completing a round of scheduling in the first queue, the scheduler transitions to the second queue to process low priority threads, then returns to the first queue. This periodic action ensures that both high and low priority threads receive execution opportunities, preventing starvation of lower priority threads while maintaining priority-based scheduling.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10467053B2Multi-thread processor with rescheduling when threads are nondispatchable
Publication Date: 2019.11.05 RENESAS ELECTRONICS CORP
  • US10467053B2 patent drawing
  • US10467053B2 patent drawing
  • US10467053B2 patent drawing

AI summary

A multi-thread processor includes a plurality of hardware threads that generates a plurality of mutually independent instruction streams, respectively and a scheduler that schedules the plurality of hardware threads.