Multi-Program Processor Scheduling for Coarse-Grained Workloads

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Solution Overview

Problem

Conventional processors are inefficient for processing coarse-grained data structures like matrices and tensors, and existing domain-specific CG-CISC processors lack support for multi-threading and multi-programming, requiring manual creation and being costly in time and effort.

Innovation Solution

A CG-CISC processor architecture that supports multi-threading and multi-programming by utilizing a combination of soft and hard logic in FPGAs, with shared architectural states and hazard detection circuits to optimize processing of coarse-grained operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional processors are used for processing coarse-grained data structures, then general-purpose computing is maintained, but processing efficiency deteriorates

Engineering Contradiction:

Improvegeneral-purpose computing capabilityVSAvoidprocessing efficiency for coarse-grained data

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The processor is segmented into multiple processing elements (PEs) that can be dynamically configured through soft logic and hard logic combinations. Each PE can be independently programmed to handle specific coarse-grained operations, allowing the system to maintain general-purpose capability while optimizing for specific data structures like matrices and tensors.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The processor architecture employs dynamic reconfigurability where processing elements can switch between different operational modes and configurations. This allows the same hardware to adapt to different computational tasks, maintaining versatility while achieving high efficiency for coarse-grained operations through runtime configuration changes.

Inventive Principle:

Principle #15Dynamics

2Productivity

If domain-specific CG-CISC processors are created manually, then processing efficiency for specific applications is improved, but device complexity and development time increase

Engineering Contradiction:

Improveprocessing efficiency for specific applicationsVSAvoidmanual creation complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The processor architecture provides a universal platform that can be configured for multiple domain-specific applications. Through a standardized interface and common hardware building blocks, the same processor design can be adapted for different applications (AI, databases, etc.) without requiring manual redesign, thus reducing development complexity while maintaining application-specific optimization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The architecture uses replicated processing elements that can be instantiated multiple times with identical or slightly modified configurations. This copying approach allows rapid deployment of domain-specific processors by replicating proven designs rather than manually creating each one, reducing both time and complexity.

Inventive Principle:

Principle #26Copying

3Device complexity

If single-program processing is used, then architectural simplicity is maintained, but resource utilization and productivity deteriorate

Engineering Contradiction:

Improvearchitectural simplicityVSAvoidresource utilization

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

Multiple program execution contexts are merged within a single processor architecture, allowing concurrent execution of multiple programs and threads. The processor combines multiple front-end circuits and back-end processing circuits that share common resources, achieving high resource utilization while maintaining relatively simple architectural principles through systematic resource sharing.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If processing elements wait for data dependencies to resolve, then computational correctness is maintained, but idle time increases

Engineering Contradiction:

Improvecomputational correctnessVSAvoididle time of processing elements

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The architecture enables continuous useful action by allowing processing elements to work on independent operations concurrently. Through multi-programming and multi-threading, when one operation is waiting for data dependencies, other processing elements can execute different operations, eliminating idle time while maintaining computational correctness through proper hazard detection and resolution mechanisms.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12585602B2Systems and methods for processor circuits

Publication Date: 2026.03.24 ALTERA CORP

AI summary

A processor circuit includes a first front-end circuit for scheduling first instructions for a first program and a second front-end circuit for scheduling second instructions for a second program. A back-end processing circuit processes first operations in the first instructions and second operations in the second instructions. A multi-program scheduler circuit causes the first front-end circuit to schedule processing of the first operations on the back-end processing circuit and causes the second front-end circuit to schedule processing of the second operations on the back-end processing circuit. A processor generator system includes a processor designer that creates specifications for a processor using workloads for a program, a processor generator that generates a first processor instance using the specifications, a processor optimizer that generates a second processor instance using the workloads, and a co-designer that modifies the program using the second processor instance.