Processor Security Checking Unit for Instruction Validation
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Solution Overview
Problem
Current computing security methods lack effective enforcement of secure boundaries for software execution, particularly in ensuring the validity and authorization of instructions and operational events within processor environments.
Innovation Solution
A processor architecture that includes an instruction fetch unit, an instruction operation unit, an operational event generator, and a security checking unit, which performs security checks based on instruction and operational event attributes to ignore, defer, or raise exceptions when security conditions are not met, thereby enforcing secure execution boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If security checking is performed for every instruction and operational event, then computing security is improved, but processor execution speed and complexity increase
Solution Approach 1:
The patent applies preliminary action by performing security checking on operational events before they are executed. The security checking unit validates the security attribute of each operational event against the instruction security attribute of the corresponding instruction in advance, preventing unauthorized operations from occurring. This proactive security verification ensures that security checks are completed prior to instruction execution, maintaining security without allowing unauthorized events to compromise the system.
Solution Approach 2:
The patent introduces a dedicated security checking unit as an intermediary component between the instruction operation unit and the operational event generator. This intermediary unit receives both the instruction with its security attributes and the operational event with its security attribute, performs the security comparison, and determines whether to allow the operational event to proceed. This mediator architecture centralizes security validation logic and prevents unauthorized operational events from directly affecting instruction execution.
2Reliability
If security checking is performed for every instruction and operational event, then computing security is improved, but device complexity increases
Solution Approach 1:
The security checking unit is designed as a universal component that handles security validation for all types of instructions and operational events within the processor. Rather than implementing separate security checking mechanisms for different instruction types or event categories, this multi-functional unit uniformly processes security attributes across the entire processor architecture, reducing overall system complexity through component consolidation.
Solution Approach 2:
The dedicated security checking unit serves as an intermediary that centralizes security validation logic, preventing the need to distribute security checking functionality across multiple processor components. This mediator approach consolidates the security verification function into a single specialized unit, making the overall processor structure more organized and manageable despite the added security functionality.
Data Source
AI summary
A secure protection method executed by a processor is provided. The secure protection method includes the following steps: Perform a security checking before or after executing an instruction according to an instruction security attribute (ISA) of the instruction and a security attribute (SA) of an operational event (OE); and ignore the OE, defer the OE, or raise a security exception when the security checking fails. The OE is generated as a side effect when the processor fetches or executes the instruction, or generated as a monitoring result on the instruction, or generated in response to an external input of the processor.