Processor With Segmented Look-Up Table Circuits
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Solution Overview
Problem
Conventional processors are inefficient in realizing both common and non-common mathematical functions, as well as fast and non-fast functions, due to wasteful use of memory resources, as they rely on a single type of memory for all functions, leading to increased costs and reduced performance.
Innovation Solution
The processor employs memory-based computation using a combination of fixed and writable look-up table circuits, with different types of memories (2-D and 3-D arrays) to categorize and store look-up tables for common and non-common, as well as fast and non-fast functions, allowing for flexible function realization post-manufacturing and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single type of memory (mask-ROM) is used to store LUTs for all functions, then device complexity is reduced, but memory resource efficiency deteriorates due to wasteful allocation for both common and non-common functions
Solution Approach 1:
The patent divides the memory system into two distinct segments: a first memory (mask-ROM) for storing LUTs of common functions and a second memory (writable memory) for storing LUTs of non-common functions. This segmentation allows each memory type to be optimized for its specific purpose, preventing the waste of high-performance memory resources on commonly used functions while ensuring efficient storage for less frequently used functions.
2Speed
If high-speed memory is used to store LUTs for all functions, then speed is improved, but cost increases due to wasteful allocation for functions that do not require high-speed implementation
Solution Approach 1:
The patent applies local quality by assigning different memory characteristics to different function categories. The first memory (mask-ROM) provides cost-effective storage for common functions, while the second memory (writable memory) provides flexible, reconfigurable storage for non-common functions. This localized optimization ensures that high-speed, high-cost memory resources are only allocated where truly necessary, rather than uniformly across all functions.
3Ease of manufacture
If a single memory type is used for all functions, then ease of manufacture is improved, but adaptability deteriorates because the processor cannot efficiently support both common and non-common functions
Solution Approach 1:
The patent creates a universal memory architecture where the first memory handles common functions and the second memory handles non-common functions. This multi-functional design allows the processor to efficiently support a broad range of mathematical functions while maintaining ease of manufacture through standardized memory interface designs and modular architecture.
4Ease of manufacture
If mask-ROM is used to store LUTs for non-common functions, then cost is reduced, but productivity deteriorates due to inefficient access speed for functions requiring fast implementation
Solution Approach 1:
The patent introduces dynamic adaptability by making the second memory writable and reconfigurable. This allows the system to dynamically load appropriate LUTs for non-common functions based on runtime requirements, optimizing both cost and productivity. The writable nature of the second memory enables flexible configuration without sacrificing access speed for functions that require fast implementation.
Data Source
AI summary
The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.