Processor Selection Logic for Interrupt Routing
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Solution Overview
Problem
Current interrupt routing methods in multi-core processor systems, particularly using logical APICs, lead to inefficiencies in power consumption and performance due to broadcasting interrupts to all processors, causing unnecessary wake-ups and interconnect traffic, as the priority information is often unreliable and not aligned with physical topology.
Innovation Solution
Creating logical APIC IDs that include a processor cluster ID and intra-cluster ID, allowing interrupts to be directed to specific processor packages, reducing unnecessary broadcasts and power consumption by only activating relevant processors, and using processor selection logic to choose an available processor to receive interrupts based on power states and priorities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are broadcast to all processors, then all processors can receive interrupt information, but power consumption increases and processors cannot stay in deep low power states
Solution Approach 1:
The patent segments the processor system into clusters with dedicated interrupt controllers. Each cluster has its own interrupt controller that can independently manage interrupts for processors within that cluster, rather than broadcasting to all processors. This segmentation allows interrupt controllers to selectively deliver interrupts only to relevant processor clusters, enabling processors to remain in deep low power states while maintaining reliable interrupt delivery to active processors.
2Adaptability or versatility
If interrupts are broadcast to all processors, then interrupt information is distributed widely, but unnecessary interconnect traffic is generated
Solution Approach 1:
The patent introduces dedicated interrupt controllers as intermediary components between interrupt sources and processors. These interrupt controllers act as mediators that receive interrupt requests and intelligently route them only to the appropriate processor clusters based on the interrupt destination. This intermediary approach maintains interrupt routing flexibility and adaptability while eliminating unnecessary interconnect traffic by preventing broadcasts to processor packages that do not need the interrupt.
3Adaptability or versatility
If logical APIC IDs are assigned without physical topology awareness, then operating system flexibility is improved, but routing complexity increases
Solution Approach 1:
The patent extracts the routing decision logic from the operating system and relocates it to dedicated hardware interrupt controllers. The interrupt controllers contain routing logic that automatically determines the correct processor cluster based on the logical APIC ID without requiring OS involvement. This extraction maintains OS flexibility in assigning logical IDs while simplifying the overall system architecture by removing the complexity of OS-based routing management.
4Reliability
If processors check every interrupt in broadcast mode, then all processors can respond to interrupts, but performance is reduced
Solution Approach 1:
The patent implements local quality by providing each processor cluster with its own dedicated interrupt controller that is optimized for delivering interrupts to that specific cluster. This localized approach allows interrupt controllers to efficiently manage and deliver interrupts to the appropriate processors without requiring all processors to check every broadcast interrupt. Processors in active clusters receive interrupts directly through their dedicated controllers, maintaining reliable response capability while improving overall system performance by eliminating unnecessary interrupt checking in idle processor clusters.
Data Source
AI summary
In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.