Processor Self-Relative Addressing for Persistent Memory Stability
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Solution Overview
Problem
The use of absolute memory addresses in non-volatile memory systems leads to conflicts and instability due to data persistence across multiple executions of an application, making it difficult to manage simultaneous access and invalid address handling, especially with the advent of persistent data structures that outlast a single application execution.
Innovation Solution
Implementing self-relative memory addressing modes in processors that allow for position-independent pointers, which store a memory offset relative to an absolute address, enabling support for invalid addresses through reserved offset values and mechanisms to handle NULL pointers without impacting performance or code size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If absolute memory addresses are used in non-volatile memory systems, then data can be stored persistently across multiple executions, but address conflicts and instability occur due to data persistence
Solution Approach 1:
The patent transforms absolute memory addresses into self-relative addresses by changing the addressing parameter. Instead of using fixed absolute addresses that cause conflicts when data persists across executions, the system uses addresses relative to a base pointer, allowing the same logical address to map to different physical locations in subsequent executions while maintaining data persistence.
2Adaptability or versatility
If self-relative memory addressing modes are implemented, then position-independent pointers are enabled, but additional instructions and code modifications are required
Solution Approach 1:
The patent makes the load and store instructions universal by enabling them to operate in both absolute addressing mode and self-relative addressing mode through a mode bit. This multi-functionality allows the same instruction set to handle different addressing schemes without requiring separate instructions, thereby reducing the increase in device complexity.
3Adaptability or versatility
If reserved offset values are used to indicate invalid memory addresses, then NULL pointer support is provided, but performance may be impacted due to additional validation checks
Solution Approach 1:
The patent implements self-service by having the processor automatically detect invalid memory addresses through the reserved offset value mechanism. When a self-relative address calculation results in the reserved offset value, the processor automatically generates a data access exception without requiring explicit software validation checks, thereby maintaining performance while supporting NULL pointers.
Data Source
AI summary
A processor may implement self-relative memory addressing by providing load and store instructions that include self-relative addressing modes. A memory address may contain a self-relative pointer, where the memory address stores a memory offset that, when added to the memory address, defines another memory address. The self-relative addressing mode may also support invalid memory addresses using a reserved offset value, where a load instruction providing the self-relative addressing mode may return a NULL value or generate an exception when determining that the stored offset value is equal to the reserved offset value and where a store instruction providing the self-relative addressing mode may store the reserved offset value when determining that the pointer is an invalid or NULL memory address.