Processor Internal Memory SHA Constants Kt

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Solution Overview

Problem

Existing SHA processors require a large number of constants and complex calculations, leading to inefficiencies due to the need for external loading of constants, which occupies the communication bus and delays calculations.

Innovation Solution

A processor with internal memory storing constants Kt, featuring a get-value W+K instruction that retrieves and adds constants directly from internal memory, reducing the need for external communication and enhancing calculation efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If constants are loaded from external memory, then the processor can access required constant values, but the external communication bus is occupied and processing time is increased

Engineering Contradiction:
Improveprocessing timeVSAvoidprocessor structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The execution unit group is designed to perform multiple functions: it can execute regular arithmetic operations and simultaneously access constants from internal memory during SHA calculations. This multi-functionality allows the processor to handle both data processing and constant retrieval without requiring separate dedicated hardware for constant storage, thus reducing overall device complexity while improving processing speed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Constants are pre-loaded into the internal memory of the processor before the SHA calculation begins. This preliminary action ensures that when the execution unit group needs to access constants during processing, they are already available in fast internal memory, eliminating the need for external bus access during critical calculation phases and significantly reducing processing time.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If constants are stored in internal memory, then external communication bus usage is reduced, but the internal memory size must be increased

Engineering Contradiction:
Improvecommunication energyVSAvoidinternal memory size
Core Design Contradiction:
Loss of energyVSVolume of stationary object

Solution Approach 1:

Instead of uniformly expanding the entire internal memory system, the patent allocates a specific portion of internal memory dedicated to storing SHA constants. This localized approach ensures that only the necessary space for constant storage is reserved, minimizing the increase in overall memory size while effectively reducing external bus communication and energy consumption.

Inventive Principle:
Principle #3Local quality

3Productivity

If a dedicated execution unit group is created for SHA operations, then SHA calculation efficiency is improved, but the processor structure becomes more complex

Engineering Contradiction:
ImproveSHA calculation efficiencyVSAvoidprocessor structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The execution unit group for SHA operations is merged with the processor's existing arithmetic logic units and memory access mechanisms. By combining SHA-specific requirements with general-purpose processing components, the patent achieves improved SHA calculation efficiency without creating entirely separate dedicated hardware, thus limiting the increase in processor structural complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3419214B1Processor with secure hash algorithm and digital signal processing method with secure hash algorithm
Publication Date: 2021.10.13 VIA ALLIANCE SEMICON CO LTD
  • EP3419214B1 patent drawingFigure 1
  • EP3419214B1 patent drawingFigure 2
  • EP3419214B1 patent drawingFigure 3

AI summary

A processor using an internal memory to store constants Kt required in a secure hash algorithm (SHA). The latency due to loading the constants Kt from an external memory, therefore, is eliminated. The processor further introduces an instruction set architecture that provides one instruction for the processor to read the constants Kt from the internal memory and perform a particular process on the read constants Kt. Thus, the SHA works efficiently.