Processor Instruction Grouping for Shared Data Buffer Reuse
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Solution Overview
Problem
In processors with multiple execution units and data buffers, shared data is transferred to multiple buffers, reducing data reusability and increasing power consumption.
Innovation Solution
A processor design with a transfer control unit that detects shared data usage and transfers it to a single data buffer corresponding to an execution unit, optimizing data reusability and reducing power consumption by minimizing redundant data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If shared data is transferred to multiple data buffers corresponding to multiple execution units, then each execution unit can access the data independently, but data reusability decreases and power consumption increases
Solution Approach 1:
Multiple data buffers corresponding to different execution units are merged into a single shared data buffer. This consolidation allows multiple execution units to access the same data through a common buffer, eliminating redundant data copies and reducing the energy consumption associated with multiple separate data transfers while maintaining data accessibility for all execution units.
2Productivity
If shared data is transferred to multiple data buffers, then data can be distributed to multiple execution units, but data reusability is reduced due to redundant transfers
Solution Approach 1:
The patent merges multiple data buffers into a single shared data buffer that serves multiple execution units. This approach maintains data distribution efficiency by allowing any execution unit to access the data through the unified buffer, while eliminating redundant data transfers that would occur if separate buffers were maintained for each execution unit, thereby reducing power consumption.
3Reliability
If multiple data buffers are provided for multiple execution circuits, then data can be cached locally at each unit, but redundant data transfers occur and power consumption increases
Solution Approach 1:
The patent combines multiple individual data buffers into a single shared data buffer that is accessed by multiple execution units. This maintains effective data caching by providing local access points for each execution unit while eliminating the redundancy of maintaining separate buffers, thereby reducing the energy consumption associated with multiple data transfer operations.
Data Source
AI summary
A processor includes execution circuits configured to execute computational instructions; a first instruction queue configured to hold the computational instructions; second instruction queues respectively provided corresponding to the execution circuits, the second instruction queues being configured to hold the computational instructions and issue the held computational instructions to the corresponding execution units; data buffers respectively provided corresponding to the execution circuits and configured to hold data used by the computational instructions; and a transfer control circuit configured to detect an address of a memory that holds data used by each of the computational instructions held in the first instruction queue, transfer, to a second instruction queue corresponding to one of the execution circuits, target computational instructions that use data at a same address, based on the detected address, and transfer the data at the same address to a data buffer corresponding to the one of the execution circuit.