Arithmetic Processor Synchronization via Shared Memory Mediator

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Solution Overview

Problem

Existing multi-core processors face challenges in efficiently synchronizing computing operations among multiple processors when processing multimedia data, particularly due to inter-dependence among data units, which degrades performance.

Innovation Solution

An operating method for computing processors that involves performing computing operations on partitioned data units, obtaining operation completion information from other processors, storing this information, and determining overall operation completion to ensure synchronized processing without repeated checks, thereby optimizing power usage and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data partitioning method is used for parallel processing, then processing speed is improved, but synchronization complexity increases due to inter-dependence among data units

Engineering Contradiction:
Improveprocessing speedVSAvoidsynchronization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a memory region as an intermediary mechanism between multiple computing processors to exchange operation completion information. This mediator enables synchronized processing of inter-dependent data units without requiring complex direct communication protocols between processors, thus maintaining high processing speed while reducing synchronization complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If operation completion information is obtained from all computing processors, then processing accuracy is improved, but power consumption increases due to repeated checks

Engineering Contradiction:
Improveoperation completion accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements a preliminary action by setting up a shared memory region before parallel processing begins. This allows operation completion information to be automatically stored and made accessible to all processors without requiring repeated active queries or checks during processing, thereby achieving accurate operation completion detection while minimizing power consumption.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If synchronization operations are performed frequently, then processing reliability is improved, but processing time increases due to additional operations

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent uses a copying mechanism where operation completion information is stored in a shared memory region that can be replicated and accessed by all computing processors simultaneously. This eliminates the need for frequent sequential synchronization operations between processors, maintaining high synchronization reliability while reducing the time lost to synchronization overhead.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11062425B2Arithmetic processor and method for operating arithmetic processor
Publication Date: 2021.07.13 SAMSUNG ELECTRONICS CO LTD
  • US11062425B2 patent drawing
  • US11062425B2 patent drawing
  • US11062425B2 patent drawing

AI summary

An operating method of a computing processor includes: performing a computing operation on a data unit assigned from among a plurality of data units that are partitioned from multi-media data; obtaining operation completion information of the computing operation performed on the data unit from among the plurality of data units, from at least one predetermined computing processor from among a plurality of computing processors; storing the operation completion information obtained from the at least one predetermined computing processor; and determining whether computing operations performed on the multi-media data have been completed, based on the operation completion information obtained from the at least one predetermined computing processor and stored, and the computing operation performed on the assigned data unit.