Processor Signature Generation for Logic Error Protection
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Solution Overview
Problem
Conventional logic error detection and correction mechanisms are inadequate in protecting against soft errors caused by neutron or alpha particle bombardment in microprocessors, particularly in high reliability and high availability systems, as they often require system reboot and are not transparently recoverable.
Innovation Solution
A processor core operates in a reliable execution mode with multiple integer execution units running in lock-step, generating and comparing signatures from result signals to detect mismatches and re-execute instructions, providing cluster-level redundancy for transparent error recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip level redundancy schemes are used to detect soft errors, then error detection capability is improved, but system recovery requires reboot and transparency is lost
Solution Approach 1:
The patent creates a copy of the critical execution path by duplicating the integer execution units and their associated signature generation logic. Multiple identical execution units process the same instruction stream in parallel, and their results are compared to detect errors. This copying approach enables error detection without requiring system reboot, as the redundant execution can be performed transparently in the background.
Solution Approach 2:
The patent applies error detection mechanisms selectively to specific execution units and their result paths rather than implementing system-wide redundancy. By placing signature generation logic and comparison circuits only in the integer execution units that require protection, the system achieves targeted error detection with minimal impact on overall system operation and transparency.
2Ease of operation
If multiple execution units operate in lock-step with signature generation and comparison, then transparent error recovery is improved, but device complexity increases
Solution Approach 1:
The patent merges the signature generation function into the existing execution unit structure, so that result signals are used both for normal execution and for error detection simultaneously. The comparison logic is integrated with the execution units, allowing error detection to occur as part of the normal execution flow without requiring separate dedicated detection hardware for each execution unit.
Solution Approach 2:
The execution units are designed to serve multiple functions: they execute instructions normally while simultaneously generating signatures for error detection. The result signals serve dual purposes - driving the execution output and feeding the signature generation logic. This multi-functionality reduces the need for separate dedicated error detection hardware.
3Measurement precision
If signature generation logic is added to each execution unit, then error detection precision is improved, but manufacturing complexity increases
Solution Approach 1:
The signature generation logic is implemented as a copy of the execution unit's result processing path, using the same result signals that already exist in the execution unit. This approach achieves high error detection precision by directly comparing the copied execution paths without requiring additional sensing or measurement hardware that would complicate manufacturing.
Solution Approach 2:
The execution units generate their own error detection signatures using their own result signals, without requiring external detection hardware. The signature generation logic is self-contained within each execution unit, using the unit's own output signals to create the comparison signatures, thereby simplifying manufacturing by eliminating the need for separate detection circuits.
Data Source
AI summary
A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each of the integer execution units in response to the result signals becoming available. The processor core also includes compare logic that may detect a mismatch between signatures from each of the integer execution units. Further, in response to the compare logic detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.