Processor Silent Store Suppression Circuit
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Solution Overview
Problem
Processor operations often result in silent stores, where data is written back to memory with no change, leading to performance and power consumption issues, as well as reduced endurance of non-volatile memory devices due to unnecessary write operations.
Innovation Solution
Hardware circuitry within the processor detects silent store operations and suppresses them, maintaining correct processor operation while reducing memory traffic and power consumption by preventing unnecessary writes to non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor writes data back to memory with unchanged values (silent stores), then the processor operation is simple and fast, but memory traffic increases and power consumption increases
Solution Approach 1:
The patent applies partial action by selectively suppressing only the redundant silent store operations while allowing necessary store operations to proceed. The store suppression mechanism compares the data to be stored with the existing cache line data and suppresses only when they match, thereby reducing memory traffic and power consumption without affecting the processor's operational speed for necessary stores.
2Reliability
If silent store operations are performed, then processor operation is maintained, but memory endurance deteriorates due to unnecessary write operations
Solution Approach 1:
The store suppression mechanism selectively prevents only the harmful redundant write operations to non-volatile memory while allowing necessary store operations to proceed. By comparing the data to be stored with the existing cache line data and suppressing only matching cases, the patent extends memory device lifespan without compromising processor operation correctness.
3Loss of energy
If silent stores are suppressed, then memory traffic and power consumption are reduced, but device complexity increases due to detection circuitry
Solution Approach 1:
The patent merges the store suppression functionality with the existing store buffer and cache control logic. The comparison between data to be stored and existing cache line data is integrated into the existing memory management pipeline, allowing the suppression mechanism to be implemented with minimal additional circuitry rather than requiring completely separate detection and control systems.
4Productivity
If silent stores are suppressed, then memory write operations are reduced, but processor performance may be impacted due to additional comparison operations
Solution Approach 1:
The patent performs the comparison between data to be stored and existing cache line data as a preliminary action before the actual store operation. This early comparison allows the processor to determine whether suppression is needed before committing to the memory write, thereby improving memory operation efficiency by avoiding unnecessary writes while the comparison overhead is minimal and integrated into the existing data flow.
Data Source
AI summary
In one embodiment, a processor has a core including at least one execution circuit, a retirement circuit, a first cache memory, and a first cache controller to control the first cache memory, where the first cache controller, in response to a store request to store a first value to a memory coupled to the processor, is to suppress the store operation when the first value matches a stored value of a cache line associated with the store operation. Other embodiments are described and claimed.