Processor Skew Alignment for Data Integrity
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Solution Overview
Problem
Existing methods for ensuring data integrity in computer systems, particularly in aircraft, are inefficient when using processor units with single or multiple cores, as they often require customized solutions that do not account for varying processor characteristics, leading to suboptimal performance and integrity checks.
Innovation Solution
A method and apparatus that utilize an integrity manager to manage data exchange between processor units in mixed integrity modes, aligning timing for synchronized processing and comparing outputs to ensure data integrity, while allowing for operation in both high and standard integrity modes, and reducing skew between processor units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If customized solutions are used for each processor type to ensure data integrity, then data integrity is improved, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent implements a universal integrity checking mechanism that works across different processor types (single-core and multi-core) without requiring customized solutions for each processor. The integrity manager uses a standardized approach with configuration files that define processor-specific parameters, allowing the same core mechanism to serve multiple processor architectures. This resolves the contradiction by making the data integrity solution universally applicable rather than requiring separate customized implementations for each processor type.
2Productivity
If parallel processing lanes are used to improve processing efficiency, then productivity increases, but maintaining synchronization and detecting skew between lanes becomes more difficult
Solution Approach 1:
The patent implements a feedback mechanism where the integrity manager continuously monitors processor lane synchronization by comparing timestamps and detecting skew between parallel processing lanes. When skew is detected, the system provides feedback to adjust timing and maintain synchronization. This resolves the contradiction by making skew detection automatic and integrated into the processing flow, allowing parallel processing to maintain both high productivity and proper synchronization monitoring.
Solution Approach 2:
The patent uses preliminary actions by pre-defining configuration files that contain processor-specific parameters, timing information, and integrity checking parameters before processing begins. This preparation allows the system to quickly detect and correct synchronization issues without complex real-time analysis, resolving the contradiction by making skew detection more manageable through advance preparation of reference data and timing parameters.
3Reliability
If strict synchronization is enforced to ensure data integrity, then reliability improves, but processing time and productivity decrease
Solution Approach 1:
The patent implements dynamic integrity checking where the system adapts the level of synchronization enforcement based on the specific processor configuration and processing requirements. Rather than applying strict synchronization universally, the integrity manager dynamically adjusts timing parameters and checking frequency based on processor capabilities and workload characteristics. This resolves the contradiction by making synchronization requirements flexible rather than rigid, maintaining data integrity while minimizing unnecessary processing delays.
Data Source
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AI summary
A method for synchronizing processor units. An external synchronizer (122) is communicated with to determine whether an undesired amount of skew (136) is present between a first processor unit (132) and a second processor unit (134) in communication with a synchronization system. The first processor unit (132) is selectively directed to perform an action (138) without generating a needed result such that the undesired amount of skew (136) between the first processor unit (132) and the second processor unit (134) is reduced when the undesired amount of skew (136) is present in the first processor unit (132). The first processor unit (132) and the second processor unit (134) are associated with each other for a high integrity mode (106) in which integrity checks are performed on corresponding messages generated by the first processor unit (132) and the second processor unit (134).