Processor Slave Free List for Physical Register Recycling Overflow
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Solution Overview
Problem
Processors with PRF renaming style face timing issues due to high rates of physical register recycling, leading to potential register recycle overflow, which can stall the processor if not managed efficiently.
Innovation Solution
A processor configuration with a master and slave free list, along with recycle circuits, where a first physical register index is routed to the master free list and a second to the slave free list upon instruction retirement, allowing for efficient recycling and handling of overflow by transferring indexes between lists as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If physical registers are recycled at a higher rate to improve processor throughput, then productivity is improved, but device complexity increases due to the need for overflow handling mechanisms
Solution Approach 1:
The free list is divided into a master free list and a slave free list. The master free list handles primary register allocation while the slave free list handles overflow registers. This segmentation allows the system to recycle up to 2N registers per cycle by distributing the recycling load across two separate structures, thereby increasing productivity without overwhelming a single free list structure.
Solution Approach 2:
The slave free list acts as an intermediary structure between the retiring instructions and the master free list. When the master free list reaches its capacity of N registers, overflow registers are temporarily stored in the slave free list, which then transfers them to the master free list when space becomes available. This intermediary mechanism enables high-rate register recycling while maintaining manageable complexity.
2Productivity
If up to 2N physical registers are recycled per processor cycle to maintain timing constraints, then productivity is improved, but loss of time occurs due to potential processor stalling
Solution Approach 1:
The system performs preliminary actions by maintaining two free lists (master and slave) in advance, allowing overflow registers to be immediately directed to the slave free list without causing processor stalls. This preliminary preparation of overflow handling capacity ensures that the processor can continuously retire up to 2N instructions per cycle without timing violations or stalling.
Solution Approach 2:
The slave free list temporarily discards overflow register indexes that cannot be immediately allocated, then recovers them by transferring to the master free list when capacity becomes available. This discarding and recovering mechanism allows the system to handle 2N register recyclings per cycle without losing timing constraints, as the slave list acts as a temporary buffer that prevents processor stalls.
Data Source
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AI summary
A processor including physical registers, a reorder buffer, a master free list, a slave free list, a master recycle circuit, and a slave recycle circuit. The reorder buffer includes instruction entries in which each entry stores physical register indexes for recycling physical registers. The reorder buffer retires up to N instructions in each processor cycle. Each master and slave free list includes N input ports and stores physical register indexes, in which the master free list stores indexes of physical registers to be allocated to instructions being issued. When an instruction is retired, the master recycle circuit routes a first physical register index stored in an instruction entry of the instruction to an input port of the master free list, and the slave recycle circuit routes a second physical register index stored in the instruction entry of the instruction to an input port of the slave free list.