Processor Slew-Ramp Control for PMIC Voltage Noise Mitigation
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Solution Overview
Problem
Voltage regulator specifications are violated when the load current ramp rate of processors exceeds the specified rate by the power management integrated circuit (PMIC), leading to large PMIC voltage noise and reliability issues due to increased minimum voltage operation.
Innovation Solution
Implementing a slew-ramp control circuit in processors to monitor and control slew ramp-up steps, throttling power consumption to mitigate voltage noise by slowly ramping up processor threads when exceeding a slew power threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the load current ramp rate of processors is increased to improve processing speed, then productivity is improved, but voltage regulator specifications are violated leading to large PMIC voltage noise
Solution Approach 1:
The patent implements dynamic control of the load current ramp rate by the processor. The processor monitors PMIC voltage noise levels and dynamically adjusts its current ramp rate to stay within specified limits. This dynamic adaptation allows the system to maintain high productivity when conditions permit while preventing voltage noise violations when the PMIC cannot handle rapid current changes.
Solution Approach 2:
The patent employs a feedback mechanism where the processor monitors PMIC voltage noise and uses this information to adjust its own current ramp rate. The PMIC provides voltage noise measurements back to the processor, which then modifies its power consumption profile accordingly. This closed-loop feedback system resolves the contradiction by allowing high productivity when voltage noise is low while preventing violations when voltage noise approaches problematic levels.
2Productivity
If the load current ramp rate exceeds PMIC specifications, then processing performance is improved, but reliability deteriorates due to increased minimum voltage operation
Solution Approach 1:
The patent implements preliminary action by having the processor proactively monitor and control its load current ramp rate before PMIC voltage noise violations occur. The processor anticipates potential violations by monitoring its own power consumption profile and PMIC voltage noise levels, adjusting its current ramp rate in advance to prevent reliability issues. This preventive approach maintains processing performance while ensuring reliability by avoiding minimum voltage operation violations.
3Object-affected harmful factors
If slew ramp-up steps are controlled to mitigate voltage noise, then PMIC voltage droops are reduced, but power consumption ramp-up becomes slower
Solution Approach 1:
The patent applies dynamic control to the slew ramp-up process, where the ramp rate is continuously adjusted based on real-time PMIC voltage noise monitoring. When voltage droops are detected or anticipated, the ramp-up speed is automatically reduced. When conditions permit, the ramp-up proceeds at maximum speed. This dynamic approach resolves the contradiction by making the ramp-up speed adaptive rather than fixed, mitigating voltage droops only when necessary while maintaining high speed when safe.
Solution Approach 2:
The patent changes the parameter of current ramp rate based on operating conditions. The processor monitors PMIC voltage noise and adjusts the slew ramp-up parameter dynamically - using slower ramp rates when voltage droops are problematic and faster ramp rates when the PMIC can handle the load. This parameter adaptation resolves the contradiction by optimizing the ramp-up speed for each specific operating condition rather than using a conservative fixed rate.
Data Source
AI summary
A method for voltage regulator noise mitigation with processor control is described. The method includes monitoring a power consumption of a sum of processor threads during thread pipeline execution. The method also includes detecting a voltage regulator noise when the power consumption exceeds a slew power threshold. The method further includes controlling slew ramp-up steps of all the processor threads according to a selected throttle control.