Processor Slice Mode Cache Memory Task Processing

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Solution Overview

Problem

Current computing systems spend a significant amount of time processing tasks at slower backing store memory speeds, which is inefficient and costly, highlighting the need for more effective utilization of cache memory capabilities to optimize task processing.

Innovation Solution

The system and method enable processors to enter a 'slice mode' where frequently used tasks or programs are retrieved from backing store memory and stored in cache memory for processing, allowing tasks to be completed at faster cache memory speeds, with the ability to dynamically reconfigure cache settings for optimal performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If tasks are processed using backing store memory, then memory capacity is sufficient, but processing speed is slow and time-consuming

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessing time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The invention segments tasks into slices that can be independently loaded into cache memory. By dividing the task into manageable slices, the system can selectively load only the necessary portions into cache, enabling fast processing while maintaining the ability to handle larger tasks through sequential slice execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary action by loading task slices into cache memory before execution. This allows the CPU to process tasks at cache speed rather than backing store speed, significantly reducing processing time. The slices are prepared and positioned in advance, enabling immediate execution at optimal speed.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If cache memory is used to speed up processing, then processing time decreases, but cache memory capacity is limited

Engineering Contradiction:
Improveprocessing timeVSAvoidmemory capacity
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The invention segments the task into multiple slices that can be sequentially loaded into the limited cache memory. This allows the small cache to handle large tasks by processing them in manageable portions, maximizing the utilization of limited cache capacity while maintaining high processing speed for each slice.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically manages cache memory by loading and unloading slices based on processing needs. The cache is actively managed to load the next slice when the current one is processed, creating a dynamic flow that maximizes cache utilization and maintains continuous high-speed processing without being constrained by fixed capacity limits.

Inventive Principle:
Principle #15Dynamics

3Productivity

If processors operate in traditional mode, then system complexity is manageable, but processing efficiency is low

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention implements a universal slice mode that can be activated on existing processors without requiring completely new hardware architecture. The same processor can operate in traditional mode for general tasks and switch to slice mode for optimized processing, providing multi-functionality that improves efficiency while managing complexity through software-based control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system changes operational parameters by transitioning between traditional processing mode and slice mode. This parameter change enables the same hardware to operate in different efficiency regimes, improving processing efficiency for specific tasks while maintaining manageable system complexity through controlled mode switching rather than fundamental architectural changes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9936209B2System and method for slice processing computer-related tasks
Publication Date: 2018.04.03 QUANTUM GROUP INC
  • US9936209B2 patent drawing
  • US9936209B2 patent drawing
  • US9936209B2 patent drawing

AI summary

Methods and systems therefrom are provided for task processing in a computing environment. The method includes identifying a program to be executed by a processor for performing at least one task and determining that a memory requirement for the program does not exceed a capacity of a cache memory for the processor to perform the task. The method also includes, in response to determining that the memory requirement for the program does not exceed the capacity of the cache memory, instructing the processor to enter into a slice mode from a current mode and execute the program in the slice mode to perform the task. In the method, the slice mode comprises copying the program from the backing store memory to the cache memory and executing the program to perform the at least one task by utilizing the program copied to cache memory.