Processor Socket Bridge for PCIe Resource Sharing
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Solution Overview
Problem
In two-socket server systems where only one CPU is used, the peripheral component interconnect express (PCIe) input/output (IO) devices connected to the second socket remain unused, leading to inefficient use of server IO resources.
Innovation Solution
Reconfiguring system interconnect links between the two CPU sockets as peripheral bus links and using a mezzanine printed circuit board to bridge electrical signals from the first CPU socket to IO devices connected to the second socket, allowing the first CPU to access these devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a 2S system is deployed with only one CPU installed, then the system can still operate with basic functionality, but the PCIe IO devices connected to the second socket remain unused resulting in diminished IO resources
Solution Approach 1:
The patent enables the first CPU socket to access IO devices originally connected to the second CPU socket by reconfiguring system interconnect links as peripheral bus links. This allows a single CPU configuration to utilize IO resources that would otherwise require a second CPU, making the system adaptable to both single-CPU and dual-CPU operations while maximizing resource utilization.
Solution Approach 2:
The patent introduces a mezzanine printed circuit board as an intermediary component that bridges the first CPU socket to the IO devices connected to the second socket. This intermediary enables signal transmission between the first CPU and second-socket-connected IO devices, allowing resource sharing without requiring both CPUs to be installed.
2Adaptability or versatility
If system interconnect links are reconfigured as peripheral bus links, then the first CPU can access IO devices connected to the second socket, but the system complexity increases due to reconfiguration requirements
Solution Approach 1:
The patent employs dynamic reconfiguration of system interconnect links, allowing the same physical links to serve different functions based on system needs. The links can operate as system interconnects when both CPUs are installed, or be reconfigured as peripheral bus links when only one CPU is installed, providing flexible adaptability without permanent structural changes.
Solution Approach 2:
The patent segments the system interconnect links into reconfigurable portions that can be independently assigned as peripheral bus links. This segmentation allows selective activation of specific link portions for IO access while maintaining the integrity of the overall system interconnect structure, reducing the complexity impact of reconfiguration.
Data Source
AI summary
Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.