Processor Socket Partitioning for Scalable Resource Management

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Solution Overview

Problem

Current motherboard architectures face challenges in efficiently managing and partitioning resources among multiple processor sockets, particularly in booting and power management, leading to limitations in scalability and independent operation of processor sockets.

Innovation Solution

The implementation of a bootable CPU architecture that allows processor sockets to operate in either non-partitioned or partitioned modes, enabling shared or isolated resource access, independent power states, and isolated communications, using hardware straps and management controllers to configure boot modes and partition settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple processor sockets are connected to share resources, then available cache size and memory resources increase, but device complexity and difficulty of managing partitioning increase

Engineering Contradiction:
Improveavailable cache size and memory resourcesVSAvoidcomplexity of managing and partitioning resources
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system is divided into multiple processor sockets that can operate independently or in combination. Each socket can be partitioned into different modes (single-socket mode, multi-socket mode, partitioned mode) allowing granular control over resource sharing and isolation, thereby managing complexity while maintaining scalability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The processor socket architecture implements dynamic mode switching between single-socket operation, multi-socket operation, and partitioned operation. This dynamic reconfiguration allows the system to adapt resource allocation and management complexity based on operational requirements, resolving the contradiction between resource quantity and management complexity.

Inventive Principle:
Principle #15Dynamics

2Reliability

If processor sockets operate in partitioned mode for independent operation, then fault isolation and power efficiency improve, but ease of operation and resource management decrease

Engineering Contradiction:
Improvefault isolationVSAvoidease of resource management
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The management controller implements universal control capabilities that can manage both partitioned and non-partitioned modes through a unified interface. This multi-functionality allows fault isolation and power efficiency benefits of partitioning while maintaining ease of operation through consistent management mechanisms across different operational modes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by stationary object

If processor sockets operate in partitioned mode with isolated communications, then power efficiency and fault isolation improve, but device complexity increases

Engineering Contradiction:
Improvepower efficiencyVSAvoidcomplexity of partition configuration
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The processor socket architecture implements self-service capabilities where each socket can independently manage its own power state and operational mode. This autonomy allows power efficiency and fault isolation through independent operation while reducing overall system complexity by eliminating the need for centralized partition management in many scenarios.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240303343A1Partitioning of processor sockets
Publication Date: 2024.09.12 INTEL CORP
  • US20240303343A1 patent drawing
  • US20240303343A1 patent drawing
  • US20240303343A1 patent drawing

AI summary

Examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. The first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.