Processor Socket Power Management via Queue Monitoring

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Solution Overview

Problem

In server systems, a significant portion of the processor remains active and powered up during PC2 power states due to other processors not being in C3 or C6 power saving states, leading to dynamic power consumption.

Innovation Solution

Implementing logic within the processor to monitor queues and FIFO buffers, blocking traffic and gating the clock signal when all queues are empty for a predetermined time, and un-gating it when requests are detected, thereby conserving power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor keeps part of it in active state during PC2 socket power state to handle resource requests from other processors, then the reliability of resource access is improved, but the power consumption increases

Engineering Contradiction:

Improveresource access reliabilityVSAvoidprocessor power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The processor is segmented into different power states for different components. While the socket enters PC2 state, individual cores can remain in C3/C6 states, and system agents can be selectively activated or deactivated based on actual resource request needs, allowing fine-grained power management

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the power state of system agents and queues based on real-time resource request patterns. When no resource requests are detected for a predetermined time, the system transitions to a lower power state; when requests are detected, it transitions to an active state, creating a dynamic response to workload conditions

Inventive Principle:

Principle #15Dynamics

2Loss of energy

If the processor enters PC2 power state when all cores are in C3 or C6 states, then the power saving is improved, but the responsiveness to resource requests deteriorates

Engineering Contradiction:

Improveprocessor power savingVSAvoidresource request response speed

Core Design Contradiction:

Loss of energyVSSpeed

Solution Approach 1:

The system performs preliminary monitoring of resource request queues even when in PC2 power state. By maintaining awareness of incoming requests through lightweight queue status checks, the processor can prepare for rapid transition to active state without actual performance degradation, thus preserving both power savings and responsiveness

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where system agents continuously monitor resource request queues and provide status information back to the power management logic. This feedback loop enables the system to detect when resource requests are present and transition from PC2 state accordingly, ensuring responsive resource access while maintaining power savings during idle periods

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10108241B2Method and apparatus for saving power of a processor socket in a multi-socket computer system

Publication Date: 2018.10.23 INTEL CORP

AI summary

Described is an apparatus comprising: a plurality of system agents, at least one system agent including one or more queues; and logic to monitor the one or more queues in at least one system agent and to cause the plurality of system agents to block traffic after satisfaction of a criterion.