Processor Soft Error Detection via Simulation-Based Error Injection
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Solution Overview
Problem
Designing computer processors to effectively detect and handle soft errors, such as bit-flips caused by radiation events, is challenging, especially in large logic state-space designs where error detection and handling logic behaves differently for various instructions and data, making simulation-based testing complex.
Innovation Solution
A method involving monitoring a baseline simulation to identify a target processing cycle for error injection, performing test simulations with injected errors, and determining if the error is detected by the processor's error-checking logic, using a software model constructed in a hardware description language like VHDL to assess soft error handling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft error detection and handling logic is incorporated into computer processor designs, then reliability against soft errors is improved, but device complexity increases
Solution Approach 1:
The patent uses simulation models (copies) of the processor design to test soft error handling without modifying the actual processor architecture. By creating virtual replicas in a software simulation environment, the invention enables thorough error detection testing while avoiding the complexity overhead of implementing physical error detection hardware in the processor itself.
2Measurement precision
If comprehensive soft error testing is performed across all instructions and data, then measurement precision of error detection is improved, but productivity of the testing process deteriorates
Solution Approach 1:
The patent performs preliminary identification of target processing cycles and error injection targets through baseline simulation before conducting actual error injection tests. This preliminary action filters and prepares the test data, so that when comprehensive testing is performed, it focuses on pre-identified critical paths and instructions, maintaining high measurement precision while improving testing productivity by avoiding brute-force testing of all possible states.
Data Source
AI summary
Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.