Processor Core Simulation State Dumping for Error Resilience
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Solution Overview
Problem
The existing methodologies for verifying architectural compliance of processor cores using sparing functions are inefficient due to the need for recovery from simulated errors, which increases simulation runtime and debugging time, as they require multiple cycles and hardware features like refreshes and logic resets.
Innovation Solution
A method involving the simulation of a processor core model at a register-transfer level, where a first state is dumped before injecting an error, and then the model is reset and initialized with the first state after detecting the error, allowing for the loading of state information from the second state to resume the simulation without recovery, thus bypassing the need for error recovery processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error recovery processes are performed to verify architectural compliance, then verification completeness is improved, but simulation runtime increases
Solution Approach 1:
The patent performs preliminary actions by dumping the processor state before error injection and storing it externally. This allows the simulation to restart from the pre-error state without executing the error recovery sequence, thereby verifying architectural compliance while significantly reducing simulation runtime.
Solution Approach 2:
The patent creates a copy of the processor state at a specific point in time and stores it in external memory. This state copy is then used to restore the processor to a known good state after error injection, eliminating the need to execute lengthy recovery procedures and reducing overall simulation time.
2Reliability
If multiple hardware features are stabilized for error recovery, then error recovery reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the state capture and restoration functionality from the complex hardware recovery mechanisms. By using external memory to store and restore processor states, the patent eliminates the need for complex hardware features like refreshes, error scan logouts, and logic resets, thereby reducing device complexity while maintaining verification reliability.
3Productivity
If state dumps are performed frequently to enable restarts, then debugging efficiency is improved, but loss of information increases
Solution Approach 1:
The patent implements a feedback mechanism where the processor state is continuously monitored and dumped to external memory at key points. This feedback loop ensures that state information is preserved externally, allowing frequent restarts without losing critical state data, thereby improving debugging efficiency while preventing information loss.
Data Source
AI summary
Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.