Multithreaded Processor Stack Overflow Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Multithreaded processors face memory challenges due to large stack allocations for numerous threads, which occupy significant space on integrated circuits and limit other functionalities.

Innovation Solution

A multithreaded processor with control registers for storing stack limit values and enable bits, allowing for adaptive memory allocation by checking stack limits and dynamically reassigned stack regions from smaller to larger sizes upon reaching predefined limits, reducing overall memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a large number of threads are supported with dedicated stack memory allocation, then thread processing capability is improved, but memory space consumption increases significantly

Engineering Contradiction:
Improvethread processing capabilityVSAvoidmemory space consumption
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges the stack memory resources of multiple threads into a shared stack region. Instead of allocating separate stack memory for each thread, a single shared stack is used by all threads, with each thread having a designated stack region within the shared stack. This consolidation dramatically reduces the total memory footprint while maintaining support for numerous concurrent threads.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic stack region allocation where the stack region for each thread is not fixed but can be adjusted based on actual usage. The system includes logic to detect when a thread's stack region is insufficient and to dynamically allocate additional stack space from other threads' unused regions, allowing the memory allocation to adapt to changing runtime conditions.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If dedicated stack memory is allocated for each thread, then stack overflow detection is simplified, but overall memory efficiency deteriorates

Engineering Contradiction:
Improvestack overflow detectionVSAvoidmemory efficiency
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The shared stack is segmented into multiple stack regions, with each region assigned to a specific thread. This segmentation allows the system to maintain simple overflow detection methods (checking boundaries) while using shared memory. Each thread has its own stack region with defined boundaries, making overflow detection straightforward despite the shared underlying memory resource.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism (stack region management logic) that mediates between the simplified overflow detection requirement and the memory efficiency goal. This intermediary layer handles the complexity of shared memory management while presenting simple boundary-checking interfaces for overflow detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If stack limit checking is performed for every procedure entry, then stack safety is improved, but processing speed deteriorates

Engineering Contradiction:
Improvestack safetyVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs stack limit checking in advance, specifically at procedure entry points, rather than continuously during execution. By checking the stack region sufficiency before entering a procedure, the system ensures stack safety while minimizing the frequency of checks to only when necessary (at procedure boundaries), thus reducing the performance overhead.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3330848B1Detection of stack overflow in a multithreaded processor
Publication Date: 2022.07.20 CISCO TECHNOLOGY INC
  • EP3330848B1 patent drawingFigure 1
  • EP3330848B1 patent drawingFigure 2
  • EP3330848B1 patent drawingFigure 3

AI summary

Embodiments are generally directed to a multithreaded processor for executing a plurality of threads, as well as an associated method and system. The multithreaded processor comprises a first control register configured to store a stack limit value, and instruction decode logic configured to, upon receiving a procedure entry instruction for a stack associated with a first thread, determine whether to throw a stack limit exception based on the stack limit value and a first predefined stack region size associated with the stack.