Processor Startup Parallel Task Execution
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Solution Overview
Problem
Current processor startup times from low power modes are prolonged due to serial execution of re-initialization and preparation tasks, leading to noticeable delays in processor readiness, while maintaining processors in a fully powered state for quick readiness results in increased power consumption.
Innovation Solution
Performing multiple processor startup tasks in parallel, including memory interface training and restoration, and using a refresh controller to maintain volatile memory state during low power modes, allowing for simultaneous PCIe bus training and processor initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor is placed in a low power mode to conserve energy, then power consumption is reduced, but the startup time increases due to serial re-initialization tasks
Solution Approach 1:
The patent applies preliminary action by saving processor state information to non-volatile memory before entering low power mode. This pre-prepared state data enables the processor to quickly restore its previous state upon wake-up, eliminating the need for time-consuming serial re-initialization tasks and reducing startup time while maintaining power savings.
Solution Approach 2:
The patent segments the startup process into parallel tasks that can be executed simultaneously. By dividing the re-initialization process into independent tasks such as restoring processor state, re-initializing memory interfaces, and re-establishing communication buses, the system reduces overall startup time without requiring the processor to remain fully powered.
2Loss of time
If multiple processor startup tasks are performed in parallel, then startup time is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a state information structure as an intermediary that stores processor state data in a format suitable for parallel restoration. This structured approach to state management facilitates coordinated parallel task execution while maintaining system controllability, reducing startup time without proportionally increasing device complexity.
Data Source
AI summary
A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.