Processor State Check Instruction for Execution Context Verification
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Solution Overview
Problem
Current data processing apparatuses, despite memory protection configurations, may experience security vulnerabilities due to bugs or malicious attacks leading to inappropriate access of sensitive code or execution in incorrect contexts, which existing techniques fail to reliably prevent.
Innovation Solution
Incorporating a processor state check instruction that compares the current processor state with a defined value, treating the instruction as a no-operation if the check succeeds and generating an illegal exception if it fails, to ensure execution occurs in the appropriate context.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory protection techniques (MMU with page tables) are used to control access to memory regions, then basic memory access security is provided, but the system remains vulnerable to bugs or malicious attacks that can lead to execution in incorrect contexts or inappropriate access to sensitive code
Solution Approach 1:
The patent applies preliminary action by inserting processor state check instructions at specific points in the code before sensitive operations are performed. These checks verify the processor is in the expected state (e.g., secure world mode, specific exception level) before executing critical code, preventing execution if the state is incorrect. This proactive approach catches context violations before they can compromise security.
Solution Approach 2:
The patent introduces an intermediary checking mechanism between the processor execution and sensitive code execution. The processor state check instruction acts as a mediator that verifies the current processor state against required state parameters, generating an exception if the check fails. This intermediary layer adds security verification without fundamentally changing the existing MMU architecture.
2Reliability
If processor state check instructions are inserted to verify execution context, then security against context violations is improved, but the instruction sequence length and processing overhead increase
Solution Approach 1:
The patent applies partial action by selectively inserting processor state check instructions only at critical points in the code where context verification is most important, rather than checking every instruction. This allows the system to verify security at key decision points and before sensitive operations while minimizing the overall impact on instruction sequence length and execution time.
3Reliability
If processor state check instructions are used to enforce correct execution contexts, then security is enhanced, but the device complexity increases due to additional exception handling requirements
Solution Approach 1:
The patent leverages the existing exception handling infrastructure of the processor, copying and adapting existing exception mechanisms to handle processor state check failures. Rather than creating entirely new exception handling pathways, the implementation reuses established exception routes and handling code, thereby adding security functionality while minimizing increases in overall device complexity.
Data Source
AI summary
A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. When the at least one runtime processor state configuration value does not match the processor state check value an exception is generated. Improved security of the data processing apparatus is thus provided.