Parallel Processor State Reload via Scan Chain Transfer
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Solution Overview
Problem
Parallel processing systems in high-availability applications like autonomous driving and financial processing face challenges in maintaining system reliability due to runtime state errors, which can lead to processor failures and erroneous output, especially when environmental conditions such as voltage fluctuations or memory errors occur.
Innovation Solution
A parallel processing system with at least three processors, state monitoring circuitry to identify runtime errors, and state reload circuitry to transfer a healthy runtime state from one processor to another, using scan chains for access and reload, and altering clock inputs and supply voltages as needed, ensuring continuous operation and high availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If runtime state monitoring and error detection is implemented in parallel processing systems, then system reliability is improved, but device complexity increases due to additional monitoring and reload circuitry
Solution Approach 1:
The patent combines multiple functions into unified circuit blocks: the state monitoring circuitry integrates error detection across multiple processors, and the state reload circuitry combines state extraction, transfer, and injection functions. This merging reduces the number of separate components needed while maintaining comprehensive monitoring and recovery capabilities, thereby improving reliability without proportionally increasing complexity.
Solution Approach 2:
The monitoring and reload circuitry are designed with universal functionality that can operate across different processor states and error conditions. The state reload circuitry can extract runtime state from any processor and inject it into any other processor, making the system adaptable to various failure scenarios without requiring specialized circuits for each case, thus balancing reliability improvement with controlled complexity.
2Reliability
If state reload is performed during runtime to correct processor errors, then system availability is maintained, but processing time is lost due to state transfer operations
Solution Approach 1:
The system maintains redundant runtime state information in multiple processors before errors occur. When a processor fails, the reload circuitry can immediately extract state from a healthy processor and inject it into the failed processor without waiting for error detection and analysis, significantly reducing the time loss while maintaining high system availability.
Solution Approach 2:
The state reload operation is designed to quickly transfer runtime state between processors using dedicated circuit pathways that bypass normal processing queues. The system rushes through the state transfer operation by directly loading the state into the failed processor's registers and memory structures, minimizing the interruption to overall system operation and reducing processing time loss.
3Manufacturing precision
If scan chains are used for state access and reload, then manufacturing precision is improved through standardized interfaces, but device complexity increases due to additional scan chain infrastructure
Solution Approach 1:
The scan chains are designed with multi-functionality, serving both traditional testing purposes and the additional function of runtime state extraction and injection. By making the scan chain infrastructure universal, the patent avoids adding separate dedicated pathways for state transfer, thereby achieving manufacturing precision through standardized interfaces without proportionally increasing device complexity.
Solution Approach 2:
The scan chain infrastructure serves itself by using the same physical pathways and control mechanisms for both testing and runtime state management operations. The existing scan chain control logic is extended to handle state extraction and injection, eliminating the need for separate dedicated infrastructure and reducing the net increase in device complexity while maintaining interface standardization benefits.
Data Source
AI summary
A parallel processing system includes at least three parallel processors, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.